JPS5694759A - Wiring forming method - Google Patents

Wiring forming method

Info

Publication number
JPS5694759A
JPS5694759A JP17252879A JP17252879A JPS5694759A JP S5694759 A JPS5694759 A JP S5694759A JP 17252879 A JP17252879 A JP 17252879A JP 17252879 A JP17252879 A JP 17252879A JP S5694759 A JPS5694759 A JP S5694759A
Authority
JP
Japan
Prior art keywords
semiconductor layer
impurity
damage
conductivity
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17252879A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6129540B2 (cs
Inventor
Masaki Okayama
Tokuro Soma
Norihiro Kusumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP17252879A priority Critical patent/JPS5694759A/ja
Publication of JPS5694759A publication Critical patent/JPS5694759A/ja
Publication of JPS6129540B2 publication Critical patent/JPS6129540B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
JP17252879A 1979-12-28 1979-12-28 Wiring forming method Granted JPS5694759A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17252879A JPS5694759A (en) 1979-12-28 1979-12-28 Wiring forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17252879A JPS5694759A (en) 1979-12-28 1979-12-28 Wiring forming method

Publications (2)

Publication Number Publication Date
JPS5694759A true JPS5694759A (en) 1981-07-31
JPS6129540B2 JPS6129540B2 (cs) 1986-07-07

Family

ID=15943589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17252879A Granted JPS5694759A (en) 1979-12-28 1979-12-28 Wiring forming method

Country Status (1)

Country Link
JP (1) JPS5694759A (cs)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923522A (ja) * 1982-07-29 1984-02-07 Matsushita Electronics Corp ドライエツチング方法
US5591300A (en) * 1995-06-07 1997-01-07 Vtc Inc. Single crystal silicon dry-etch endpoint based on dopant-dependent and thermally-assisted etch rates

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923522A (ja) * 1982-07-29 1984-02-07 Matsushita Electronics Corp ドライエツチング方法
US5591300A (en) * 1995-06-07 1997-01-07 Vtc Inc. Single crystal silicon dry-etch endpoint based on dopant-dependent and thermally-assisted etch rates

Also Published As

Publication number Publication date
JPS6129540B2 (cs) 1986-07-07

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