JPS574141A - Wiring structure in semiconductor device - Google Patents
Wiring structure in semiconductor deviceInfo
- Publication number
- JPS574141A JPS574141A JP7849280A JP7849280A JPS574141A JP S574141 A JPS574141 A JP S574141A JP 7849280 A JP7849280 A JP 7849280A JP 7849280 A JP7849280 A JP 7849280A JP S574141 A JPS574141 A JP S574141A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layers
- metal
- wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000010410 layer Substances 0.000 abstract 9
- 239000002184 metal Substances 0.000 abstract 5
- 230000003647 oxidation Effects 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 abstract 3
- 239000011229 interlayer Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To reduce a height difference in the layers and prevent a cutting of the upper layer wirings by a method wherein inter-layer insulative film of Si-gate MOS device is of two layers, a metal layer contacted with a substrate area is arranged between the layers, and the metal layer is connected to the upper layer wirings. CONSTITUTION:Gate metal 6 composed of gate film 5 and poly-Si or Mo is arranged on, for example, P type substrate 1 divided by oxidation film 2, the wiring 7 is arranged on the oxidation film 2, thereafter PSG film 20 is accumulated to about 1/2 of a required thickness as an inter-layer film. Hot heat treatment is applied to have a diffusion N type layers 3, 4 in a source drain area, then an opening is made in the film 20, and a contact metal for example Al is extended over the oxidation film 2 to be formed thereon. Then, the insulation film 23 is formed to show a thickness which is substantially the same as that of the film 20, a contact hole is formed in the film 23, Al wiring 25 in the upper layer is formed, and connected to the contact metal 22. Thus, it is possible to reduce a height difference between the contact areas, so that a cutting of Al wiring may be prevented and its reliability in operation may also be improved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7849280A JPS574141A (en) | 1980-06-10 | 1980-06-10 | Wiring structure in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7849280A JPS574141A (en) | 1980-06-10 | 1980-06-10 | Wiring structure in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS574141A true JPS574141A (en) | 1982-01-09 |
Family
ID=13663467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7849280A Pending JPS574141A (en) | 1980-06-10 | 1980-06-10 | Wiring structure in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS574141A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4994402A (en) * | 1987-06-26 | 1991-02-19 | Hewlett-Packard Company | Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device |
-
1980
- 1980-06-10 JP JP7849280A patent/JPS574141A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4994402A (en) * | 1987-06-26 | 1991-02-19 | Hewlett-Packard Company | Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device |
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