JPS5779634A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5779634A
JPS5779634A JP55155203A JP15520380A JPS5779634A JP S5779634 A JPS5779634 A JP S5779634A JP 55155203 A JP55155203 A JP 55155203A JP 15520380 A JP15520380 A JP 15520380A JP S5779634 A JPS5779634 A JP S5779634A
Authority
JP
Japan
Prior art keywords
layer
magnesia spinel
spinel layer
single crystal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55155203A
Other languages
English (en)
Inventor
Masaru Ihara
Yoshihiro Arimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55155203A priority Critical patent/JPS5779634A/ja
Publication of JPS5779634A publication Critical patent/JPS5779634A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP55155203A 1980-11-06 1980-11-06 Manufacture of semiconductor device Pending JPS5779634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55155203A JPS5779634A (en) 1980-11-06 1980-11-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55155203A JPS5779634A (en) 1980-11-06 1980-11-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5779634A true JPS5779634A (en) 1982-05-18

Family

ID=15600747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55155203A Pending JPS5779634A (en) 1980-11-06 1980-11-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5779634A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444014A (en) * 1994-12-16 1995-08-22 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device
JPH08186165A (ja) * 1994-12-19 1996-07-16 Korea Electron Telecommun Ｓｏｉ基板の製造方法およびこれを利用した双極子トランジスターの製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444014A (en) * 1994-12-16 1995-08-22 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device
JPH08186165A (ja) * 1994-12-19 1996-07-16 Korea Electron Telecommun Ｓｏｉ基板の製造方法およびこれを利用した双極子トランジスターの製造方法

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