JPS5796552A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5796552A JPS5796552A JP55173535A JP17353580A JPS5796552A JP S5796552 A JPS5796552 A JP S5796552A JP 55173535 A JP55173535 A JP 55173535A JP 17353580 A JP17353580 A JP 17353580A JP S5796552 A JPS5796552 A JP S5796552A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- phosphorous
- glass layer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To avoid failures such as a level discontinuity by stage of a wiring by a method wherein a compound film of a silicone oxide film and a phosphorous glass film is adopted as a layer insulating film, so that a smooth layer insulating film can be formed without deteriorating the reliability of insulation. CONSTITUTION:An Si oxide film 310 is formed on a surface of a MOS semiconductor device which is composed by forming a diffused layer 307 which is to be a source and drain and a gate electrode 309 on a surface of a semiconductor substrate 301 such as Si. Then a thin glass layer 311 with phosphorous density less than 11% is formed. The entire wafer is thermal processed, so that a difference in level is relieved by smoothening the phosphorous glass layer 311 like a slope 3110. A contact hole with a vertical wall is formed by hightly oriented dry etching with gas containing fluorine using a resist 312 as a mask. Then by wet-etching the surcumference of the contact hole is made smooth like dot line 903 because etching speed of the phosphorous glass layer is high.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55173535A JPS5796552A (en) | 1980-12-09 | 1980-12-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55173535A JPS5796552A (en) | 1980-12-09 | 1980-12-09 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5796552A true JPS5796552A (en) | 1982-06-15 |
| JPS6353695B2 JPS6353695B2 (en) | 1988-10-25 |
Family
ID=15962323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55173535A Granted JPS5796552A (en) | 1980-12-09 | 1980-12-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5796552A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6237936A (en) * | 1985-08-09 | 1987-02-18 | インタ−ナショナル．ビジネス．マシ−ンズ．コ−ポレ−ション | Formation of openings simultaneously in layers different in thickness |
-
1980
- 1980-12-09 JP JP55173535A patent/JPS5796552A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6237936A (en) * | 1985-08-09 | 1987-02-18 | インタ−ナショナル．ビジネス．マシ−ンズ．コ−ポレ−ション | Formation of openings simultaneously in layers different in thickness |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6353695B2 (en) | 1988-10-25 |
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