JPS58121642A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS58121642A
JPS58121642A JP57002800A JP280082A JPS58121642A JP S58121642 A JPS58121642 A JP S58121642A JP 57002800 A JP57002800 A JP 57002800A JP 280082 A JP280082 A JP 280082A JP S58121642 A JPS58121642 A JP S58121642A
Authority
JP
Japan
Prior art keywords
layer
single crystal
insulator
substrate
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57002800A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6325707B2 (mo
Inventor
Michiharu Tanabe
田部　道晴
Masaaki Sato
政明 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57002800A priority Critical patent/JPS58121642A/ja
Publication of JPS58121642A publication Critical patent/JPS58121642A/ja
Publication of JPS6325707B2 publication Critical patent/JPS6325707B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
JP57002800A 1982-01-13 1982-01-13 半導体装置の製造方法 Granted JPS58121642A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57002800A JPS58121642A (ja) 1982-01-13 1982-01-13 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57002800A JPS58121642A (ja) 1982-01-13 1982-01-13 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58121642A true JPS58121642A (ja) 1983-07-20
JPS6325707B2 JPS6325707B2 (mo) 1988-05-26

Family

ID=11539443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57002800A Granted JPS58121642A (ja) 1982-01-13 1982-01-13 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58121642A (mo)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS598346A (ja) * 1982-06-30 1984-01-17 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン 完全に誘電体分離された集積回路の製造方法
JPS6294254A (ja) * 1985-10-17 1987-04-30 Bandou Kiko Kk ガラス板の研削機械
US4925805A (en) * 1988-04-05 1990-05-15 U.S. Philips Corporation Method of manufacturing a semiconductor device having an SOI structure using selectable etching
JP2007180570A (ja) * 2007-02-14 2007-07-12 Toshiba Corp 半導体装置および半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS598346A (ja) * 1982-06-30 1984-01-17 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン 完全に誘電体分離された集積回路の製造方法
JPS6294254A (ja) * 1985-10-17 1987-04-30 Bandou Kiko Kk ガラス板の研削機械
US4925805A (en) * 1988-04-05 1990-05-15 U.S. Philips Corporation Method of manufacturing a semiconductor device having an SOI structure using selectable etching
JP2007180570A (ja) * 2007-02-14 2007-07-12 Toshiba Corp 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
JPS6325707B2 (mo) 1988-05-26

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