JPS5842251A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS5842251A
JPS5842251A JP56140773A JP14077381A JPS5842251A JP S5842251 A JPS5842251 A JP S5842251A JP 56140773 A JP56140773 A JP 56140773A JP 14077381 A JP14077381 A JP 14077381A JP S5842251 A JPS5842251 A JP S5842251A
Authority
JP
Japan
Prior art keywords
film
oxidation
field
groove
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56140773A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6355780B2 (2
Inventor
Hiroshi Iwai
洋 岩井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56140773A priority Critical patent/JPS5842251A/ja
Publication of JPS5842251A publication Critical patent/JPS5842251A/ja
Publication of JPS6355780B2 publication Critical patent/JPS6355780B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
JP56140773A 1981-09-07 1981-09-07 半導体装置の製造方法 Granted JPS5842251A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56140773A JPS5842251A (ja) 1981-09-07 1981-09-07 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56140773A JPS5842251A (ja) 1981-09-07 1981-09-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5842251A true JPS5842251A (ja) 1983-03-11
JPS6355780B2 JPS6355780B2 (2) 1988-11-04

Family

ID=15276411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56140773A Granted JPS5842251A (ja) 1981-09-07 1981-09-07 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5842251A (2)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939951A (en) * 1987-07-14 1990-07-10 Nihon Plast Co., Ltd. Impact absorbing structure for use in steering wheels and the like
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5981357A (en) * 1996-04-10 1999-11-09 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology
WO2001084602A3 (en) * 2000-05-03 2002-04-04 Maxim Integrated Products Method of forming a shallow and deep trench isolation (sdti) suitable for silicon on insulator (soi) substrates
JP2006319296A (ja) * 2005-05-11 2006-11-24 Hynix Semiconductor Inc 半導体素子の素子分離膜およびその形成方法
EP1182699A3 (de) * 2000-08-22 2007-01-31 Infineon Technologies AG Verfahren zur Bildung eines dicken dielektrischen Gebietes in einem Halbleitersubstrat

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10960894B2 (en) * 2018-12-13 2021-03-30 Waymo Llc Automated performance checks for autonomous vehicles
JP7165093B2 (ja) 2019-03-29 2022-11-02 本田技研工業株式会社 車両制御システム

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939951A (en) * 1987-07-14 1990-07-10 Nihon Plast Co., Ltd. Impact absorbing structure for use in steering wheels and the like
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5981357A (en) * 1996-04-10 1999-11-09 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US6353253B2 (en) 1996-05-02 2002-03-05 Advanced Micro Devices, Inc. Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
WO2001084602A3 (en) * 2000-05-03 2002-04-04 Maxim Integrated Products Method of forming a shallow and deep trench isolation (sdti) suitable for silicon on insulator (soi) substrates
EP1182699A3 (de) * 2000-08-22 2007-01-31 Infineon Technologies AG Verfahren zur Bildung eines dicken dielektrischen Gebietes in einem Halbleitersubstrat
JP2006319296A (ja) * 2005-05-11 2006-11-24 Hynix Semiconductor Inc 半導体素子の素子分離膜およびその形成方法

Also Published As

Publication number Publication date
JPS6355780B2 (2) 1988-11-04

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