JPS5910580B2 - hand tai souchi no seizou houhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and provides a method for improving multilayer wiring in manufacturing a semiconductor device.

In an example of a semiconductor device such as a bipolar IC, electrode wiring is performed after functional elements are formed, but in order to achieve a high degree of integration of the engineering circuit, so-called multilayer wiring in which multiple wiring layers are formed with electrical insulating layers interposed is applied. be done.

Sharp steps and protrusions in the surface structure during the manufacturing process of ICs become more complex as they are further superimposed and subjected to processing such as film deposition, leading to a loss of the electrical characteristics of the IC. . In the manufacture of ICs with multilayer wiring structures, low-temperature silicon oxide films are often used as electrical insulating layers, but this tends to cause abnormal growth at the above-mentioned steep steps and protrusions, so it is difficult to stack layers on top of these. There is a serious drawback in that it causes accidents such as disconnection in the wiring layer formed by the process. Description f will be explained with reference to FIG. First, aluminum is vapor-deposited on one main surface of the substrate 1 and then photo-etched to form the first wiring layers 2, 2' in a predetermined pattern (Fig. a).
). Although the illustrated substrate 1 is shown with the details of its cross section omitted, the substrate referred to here is, for example, a silicon substrate on which an electrode region is formed and whose main surface is covered with a SiO2 film. The above S in the case where wiring is applied
iO2 film, electrode region, and S for deriving the electrode region
It is assumed that the iO2 film is provided with apertures and the like. Next, an example of CVD (Chemical Vapor Deposit)
An electrically insulating layer 3 of SiO2 is deposited by the method (FIG. b). In the above, a portion of the layer 510 (indicated by the arrow in FIG. b) deposited on the shoulder end in the width direction of the first wiring layer has abnormal growth and is poor in film quality. Next, aluminum is deposited on top of the above, and a second wiring layer 4 having a predetermined pattern is formed by photolithography (FIG. c). Furthermore, the situation of the main part of the above-mentioned figure c is shown in figure d. As is clear from the figure, in the deposited SiO2 layer, the part where it was deposited on the shoulder end in the width direction of the first wiring layer was abnormally grown, so the layer was deposited on top of this part. The second wiring layer 4 thus formed has a cutout portion 5 in a portion thereof. For this reason, the second wiring layer has a high resistance, and has the disadvantage of leading to accidents such as disconnection. As a countermeasure to the above, the growth temperature of the SiO2 layer was set to 7
Setting the temperature as low as 00° C. is suitable for the above-mentioned problems, but when the wiring layer is made of aluminum, it has the disadvantage that it is diffused into the substrate by the above-mentioned heating, impairing the electrical characteristics of the semiconductor device. There is also a means of preventing abnormal growth of the SiO2 layer by applying taper etching to the photolithography used to form the wiring layer, but taper etching has the disadvantage of poor reproducibility.

Therefore, S! in Figure 1b! 02 Layer 3 is made sufficiently thick, that is, the layer thickness exceeds the wiring layer 2 by using SiO as shown in FIG. 1e.
A method is known in which two layers 3' are deposited and etched to the position shown by the dashed line to form a flat surface as shown in FIG. 1f.

However, the SiO2 layer 3'' formed by the above-mentioned means
On the exposed surface of the wiring layer, at the shoulder end in the width direction, SiO
The CVD growth in No. 2 is abnormal and the film quality is inferior, as already stated.

The etched surface cannot reach a flat surface in areas of poor film quality, resulting in the formation of complex concave surfaces, which has the drawback of adversely affecting subsequent processes. Therefore, the drawbacks such as the formation of a missing portion in the second wiring layer 4 formed thereon cannot be solved. The present invention improves the drawbacks of the conventional semiconductor device manufacturing method described above, and makes it possible to easily form high-quality multilayer wiring in the manufacture of C, which requires multilayer wiring.

The method for manufacturing a semiconductor device according to the present invention includes forming a first wiring layer on a substrate, and then fluidly applying a solution containing silica to form a silica film.
By depositing a first electrically insulating layer thinner than the wiring layer using the CVD method, etching the convex portions of the exposed surface of this electrically insulating layer, and then depositing a second electrically insulating layer. This method is characterized by forming multilayer wiring.

An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 2a, a first aluminum layer is formed on one main surface of the substrate
wiring layers 2 and 2' are formed.

Note that the substrate illustrated above shows details of the cross section, such as the electrode area in the silicon substrate, and the SlO between the wiring layer and the substrate.
2 film, the openings in the SlO2 film for leading out the electrode area, etc. are omitted, and the substrate 1 shown in the drawing is simply used. wear it. This silica film is formed by applying an example of 0CD (trade name, manufactured by Tokyo Ohka KK, containing 11% (weight) SiO2) using a spinner (rotation speed: 4200 RPM), and then baking it in air at 220°C for 10 minutes. In this way, the adhesion is strengthened and a layer thickness of approximately 3000 λ is obtained. or 1gr. of P2O5. Grade 5.9% silica film 1
007n1 solution may be used, and a layer thickness of about 2000λ can be obtained by applying the same spin coating and heat treatment as described above. Next, as shown in figure b, the first SiO2 layer 1
3 is deposited by CVD method as an example.

Since this SiO2 layer is formed thinner than the wiring layer, it protrudes from the upper part of the substrate to form a convex portion 13a above the wiring layer. Furthermore, after a resist film 6 for photolithography is deposited, the convex portions of this resist film are removed. Next, using an example of NH4F, SiO? The convex portion 13a of the first SlO2 layer 13 is etched, resulting in the result as shown in Figure c. Here, the first SiO2 layer 13 has a good film quality in the vicinity of the wiring layer, so it is generally about 1 to 2 μ thick, about 10 to 20 μm thick.
The above is sufficient. In addition, the etching pattern for the SiO2 layer is, for example, S in the electrode part.
A mask for photoetching was prepared from the information obtained during the formation of the 1O2 layer, and the photolithography was carried out using this mask.

Next, a second SiO2 layer 13' is deposited as shown in Figure d.
Furthermore, a second wiring layer 14 is deposited.

In other words, this second SiO2 layer 13' completes electrical insulation between both the first and second wiring layers, and also improves the flatness of the exposed surface, making it easy to arrange the second wiring layer with high quality. will be achieved. According to this invention, C of multilayer wiring
To form a wiring layer, first a wiring layer is provided on the substrate, then a viscous solution containing silica is applied to form a silica film, and then a SiO2 film is layered and deposited using the CVD method. A significant advantage is that the film quality is uniform.

In contrast, in conventional methods, the electrically insulating layer is deposited on both the oxide film and the wiring layer of the substrate. Therefore, in this way, Si is deposited by CVD on the different surfaces of the adherends.
It was confirmed through experiments that there are differences in the layer quality of the O2 layer (electrical insulating layer). That is, FIGS. 3A and 3B, which are photographs, show the adhesion state according to the present invention, and FIG. 3A is a perspective view (partial cross section).
, and b show cross sections, respectively.

In the figure, the transition part from the part of the first electrically insulating layer adhered to the main surface of the substrate to the wiring layer has a gentle, obtuse angle, and the layer quality is as homogeneous as that of the main surface of the board. For reference, please compare with the conventional method shown in FIG. In the conventional type, the transition portion is not only acute but also significantly bent. Furthermore, the layer quality is also different from that of the main surface portion of the substrate. FIG. 5a shows the features of the shape of the above-mentioned part according to the present invention, and FIG. 5b shows a cross-sectional view of the shape according to the conventional method. As mentioned above, according to this invention, the first
Since the electrically insulating layer is deposited only on the silica film, its layer quality is uniform and its shape is smooth. Furthermore, the convex portions are etched to make them even smoother, and then the second wiring layer is deposited, so the quality of this layer is uniform and the etching for patterning is also more accurate. . Therefore, there is an advantage that the above-mentioned stacked multilayer wiring can be achieved easily and at the same time with high quality. It is also very effective in increasing the degree of integration of ICs.

[Brief explanation of the drawing]

1A to 1C are cross-sectional views showing a conventional IC manufacturing method of a semiconductor device step by step, FIG. 1D is a sectional view further showing a part of FIG. 2A to 2D are cross-sectional views showing step-by-step a manufacturing method of one embodiment of a semiconductor device, and FIGS. The situation in the vicinity of the wiring layer in an IC according to an embodiment of the invention is shown in photographs (magnification: 3000x), where a is a partially perspective view of a cross section, and is a cross-sectional view, respectively. Fig. 4 shows a wiring layer in a conventional IC. 5A is a cross-sectional view for further explaining the state of the vicinity of the wiring layer shown by the photograph of FIG. 3; FIG. 4B is a sectional view for further explaining the state of the vicinity of the wiring layer shown by the photograph of FIG. 4. Note that the same reference numerals in the figures indicate the same or corresponding parts, respectively. 1...Silicon substrate, 2...
・First wiring layer (aluminum layer), 11...
Silica film, 13...first SlO2 layer,
13/... second SiO2 layer, 14...
- Second wiring layer (aluminum layer).

Claims (1)

[Claims] 1. A step of depositing and forming a first wiring layer on the substrate, a step of fluidly applying a solution containing silica to the exposed portions of the substrate and the exposed portion of the wiring layer to form a silica film, and a step of forming a first wiring layer on the silica film. a step of depositing a first electrically insulating layer thinner than the wiring layer by a CVD method, a step of etching the convex portion of the exposed surface of the electrically insulating layer, and a step of depositing a second electrically insulating layer, A method for manufacturing a semiconductor device, comprising the step of depositing a second wiring layer on the electrically insulating layer.