JPS59227143A - 集積回路パツケ−ジ - Google Patents

集積回路パツケ−ジ

Info

Publication number
JPS59227143A
JPS59227143A JP58101317A JP10131783A JPS59227143A JP S59227143 A JPS59227143 A JP S59227143A JP 58101317 A JP58101317 A JP 58101317A JP 10131783 A JP10131783 A JP 10131783A JP S59227143 A JPS59227143 A JP S59227143A
Authority
JP
Japan
Prior art keywords
integrated circuit
chip
lead
terminal
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58101317A
Other languages
English (en)
Inventor
Seiichi Nishikawa
誠一 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP58101317A priority Critical patent/JPS59227143A/ja
Publication of JPS59227143A publication Critical patent/JPS59227143A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は集積＠Ｉ＠　＃Ｒツケージに関する。
近年電子回路の代名詞的存在となった集積回路は、半導
体素子等により構成されたＩＣチップ、このＩＣチップ
の端子を外部に接続するため及び集積回路を機械的に支
持するためのリード、ならびＫＩＣチップの封止および
ＩＣチップとリードとの接続部分の封止、さらに集積回
路全体のノ・ウジングとしてのｐＲツケージからなって
いる。
このパッケージには樹脂タイプのものとセラミックタイ
プのものがあり、まず樹脂タイプのものは第１図または
第２図に示すような構造となってａｅツケージ（ＤＩＰ
）と呼ばれ、ＩＣチップ１をリードフレーム２上に設置
してＩＣチップの端子とリードフレーム２のリードとを
ワイヤメンディングした上でＩＣチップ１およびＩＣチ
ップ１とリードとの接続部分を樹脂モールド３により封
止してなる。また第２図のものはフラット／ぞツヶージ
と呼ばれ、リードフレーム２のリードが平面内に引き出
されている。
一方セラミックタイプのものは第３図（ａ）　、　（ｂ
）Ｋ示すように、ＩＣチップ１をセラミック基板４上忙
設置してＩＣチップ１の端子をセラミック基板４の周縁
に設けたメタライズ電極５＆Ｃワイヤボンデイングし蓋
６ｔ−被せてなるものである。
これら樹脂タイプおよびセラミックタイプの集積回路は
それぞれ一長一短があるが、コスト的に見た場合忙は樹
脂タイプのものが遥か忙利用し易い。
しかしながら、樹脂タイプのものはリードが集積回路の
側方に出るため、いくつかの集積回路を所定面領域内に
並置しようとする場合に実装密度が上げられないという
欠点がある。
本発明は上述の点を考慮してなされたもので、リードを
頂面、底面の少くとも一方に設けてなる樹脂モールド型
巣積回路ｐＲツケージを提供するものである。
以下第４図乃至第１１図を参照して本発明を実施例につ
き説明する。
第４図は本発明の集積回路忙用いるリードフレームの一
例を平面形状で示したものであり、中央部ＫＩＣチップ
１を設置するためのＩＣチッゾマウント部２ａが設けら
れ、このマウント部２ｍ’％７取囲んでリード２ｂが８
個設けられている。リード２ｂの１つはマウント部２色
に連結されている。
そして、各リード２ｂの中央部には端子２ｃが設けられ
ている。この端子２ｃはリードフレーム２の平面に対し
垂直方向に突出していて、後に樹脂モールド３が施され
た状態で樹脂表面から露出するよ５になっている。
そして切断線ＣＬで切断されることにより１つの集積回
路が出来上る。
第５図（ａ）　、　（ｂ）は本発明に係る集積回路ノｅ
ツケージの外観形状を示したもので、同図（ａ）はリー
ド１２、ｂの樹脂モールド側方への突出部分を切断した
もの、同図（ｂ）は適当の長さだけり−ド２ｂｔ残した
ものを示している。これらは何れも外部回路等との接続
を主として端子２ｅＫより行うからり−ド２ｂの長さは
せいぜい集積回路を固定するために必要な程度でよく、
また固定全接着等の他の手段によって行うことにより集
積回路の実装密度を向上し得る。なお、リード２ｂを集
積回路の同定に利用すれば剥落防止効果が得られる。
第６図（ａ）　、　（ｂ）　、　（ｅ）は第４図のリー
ドフレームを用いて構成した本発明に係る集積回路の側
断面形状を示したもので、同図（ａ）は端子Ｃが樹脂モ
ールド３の樹脂表面から突出した例、同図（ｂ）は端子
Ｃが樹脂表面と同一面をなす場合、同図（ｅ）は端子Ｃ
が樹脂表面より窪んでいる場合をそれぞれ示している。
各場合とも端子２Ｃの表面には金メッキ等を施しておく
ことが好ましい。
これら各場合ともＩＣテップ１はリードフレーム２に対
し端子２ｅと反対側に設けである。これは、ＩＣチップ
１會端子２ｃと同−例に設けた場合、端子２ｃの突出寸
法をＩＣチップ１の高さよりも大としなければならず、
それ忙はリードフレーム２の板厚をかなり大にする等の
対策が必要なためである。したがってマウント部２ａを
リード２ｂより一段下げる等のＩＣチッゾｌの頂部がよ
り低くなる手段を講じるか、あるいは端子２ｃをリード
フレーム２とは別個［Ｊｌｌｉ作しリードフレーム２上
に付着させる方法を採るかすれば、ＩＣチップ１と端子
２ｃとをリードフレーム２の同−例に配しても差支えな
い。
第７図（ａ）　、　（ｂ）はリードフレーム２を折曲げ
成形すること釦より端子２ｅｆ形成した場合の集積回路
の側断面形状を示したもので、同図（ａ）が端子２ｃの
突出したもの、同図（ｂ）が端子２ｃが突出しないもの
を示している。
第８図（ａ）　、　（ｂ）は上述のワイヤボンディング
と異なり、ギヤングダンディングによりＩＣチップ１と
リード２ｂとを接続してなる集積回路の例を示しており
、同図（＆）の場合は端子２ｃが樹脂モールド３の樹脂
表面から突出した例、同図（ｂ）の場合は同一面をなす
例である。図示しないが９６図（ｃ）の例のように端子
２ｃが樹脂表面より窪んだものも勿論可能である、 第９図（ａ）　、　（ｂ）はギヤングボンディングによ
る第７図（ａ）　、　（ｂ）に相当する構造の側断面形
状を示したものであり、ＩＣチップ１が直接リード２ｂ
に接続される外は第７図と同様である。
第１（１図（ａ３　、　（ｂ）は第９図（ａ）　、　（
ｂ）の集積回路の平面形状を示したもので、リード２ｂ
のＩＣチップ１寄りの端ＳはＩＣチップ１の端子に位置
合わせできるように端部同士が接近し且つ尖っており、
ＩＣチップ１の端子に直接接続される。そしてリード２
ｂの・ぞツケージから突出した部分は短（成形されてい
る。
第１１図（ａ）　、　（ｂ）は上述の集積回路なＩＣカ
ードすなわちプラスチックカードに集積回路を組込んだ
もので、例えば銀行の自動支払機等において使用される
ものに＃Ｉ込んだ例を示している。上述の集積回路ＩＯ
はプラスチックカード加の表面所定領域に同図（ａ）に
示すように配される。そして組込構造を断面で示したの
が同図（ｂ）であり、集積回路】０は接着剤等によりカ
ードかの一方のオーバーレイ５に固着される。カード加
は一対のセンターコア４゜４が貼り合わせたもの又は一
枚のセンターコアに一対のオーバーレイ５．５が貼着さ
れてなり、センターコア４とオーバーレイ５との間に印
刷が施されている。カードかの全厚みは０．６〜０．８
　言禦であり、集積回路ｌＯはそれよりも薄く製作でき
るから、カードかの面と集積回路１０の面を同一面とす
ることは容易である。
このカードは所定のカード処理機に挟入されると端子２
ｃを介してカード処理機と集積回路との間での信号授受
が行われ、カード処理される。
本発明は上述のように、集積回路の頂面等に端子金有す
るようにしたため、％に、ＩＣカード組込み忙適した集
積回路が得られる。そして、このＩＣカードの組込み時
にはリード２ｂが集積回路制御から突出したものを用い
れば剥落防止のための補強が行われる。またカード以外
に適用しても集積回路の実装密度を向上することがｒ：
ぎる。
【図面の簡単な説明】
第１図（ａ）　、　（ｂ）および第２図は従来の樹脂タ
イプ集積回路の構造説明図、第３図（ａ）　、　（ｂ）
は同じくセラミックタイプ集積回路の構造説明図、第４
図は本発明に係る集積回路製作に用いるエツチングで端
子を設けたリードフレームの一例を示す平面図、第５図
（ａ）　、　（ｂ）は本発明に係る集積回路の外観形状
を示す図、第６図（ａ）　、　（ｂ）　、　（ｃ）は第
４図のリードフレームを用いて構成した集積回路の断面
構造を示す図、第７図（ａ）　、　（ｂ）は折曲げによ
り端子を形成したリードフレームによる集積回路の断面
構造を示す図、第８図（ａ）　、　（ｂ）および第９図
（ａ）　、　（ｂ）はギヤングボンディングによる集積
回路の断面構造を示す図、第１Ｏ図（ａ）　、　（ｂ）
はギヤングボンディングによる集積回路の平面構造を示
す図、第１１図（ω、（ｂ）は本発明に係る集積回路を
ＩＣカードに適用した場合の説明図である。 １・・・ＩＣチップ、２・・・リードフレーム、２１Ｌ
・・・ＩＣチップマクント部、２ｂ−リード、２ｃ・・
・端子、３・・・樹脂モールド、４・・・セラミック基
板、５・・・メタライズ電極、６・・−蓋、ＩＯ・・・
集積回路、Δ）・・・カード。 出願人代理人　　　猪　股　　　　清 （。）　第５図 Ｏ 第６図 （Ｃ） Ｃ １ 第７図 第８図 Ｃ 第９図 （ａ） （ｂ） Ｃ 第１Ｏ図 ｂ ｂ− 手続補正書 昭和閏年７月２日 特許庁長官　　　若　杉　和　夫　殿 １、事件の表示 昭和閏年特許願第１０１３１７号 ２、発明の名称 一積回路パッケージ ３、補正をする者 事件との関係　特許出願人 （２８９）大日本印刷株式会社 ７、補正の対象 明細書および図面 ８、補正の内容

Claims (1)

  1. 【特許請求の範囲】 １、リードフレームのリード部にＩＣチップが接続され
    た上で樹脂モールドが施され、次いで前記リードフレー
    ムの不要部分が切断されることにより構成される集積回
    路において、前記リードフレームのリード部を樹脂モー
    ルドの表面に露出させたことを特徴とする集積回路。 ２、特許請求の範囲第１項記載の集積回路において、前
    記リード露出部分は金メッキ層で被われてなる集積回路
    。 ３、特許請求の範囲第１項記載の集積回路忙おいて、前
    記リード露出部分はニッケルメッキ層および金メッキ層
    の２層メッキ層で被われてなる集積回路。 ４、特許請求の範囲第１項記載の集積回路においワイヤ
    ダンディングにより接続されてなる集積回路。 ５、特許請求の範囲第１項記載の集積回路におい文、前
    記リードフレームと前記ＩＣチップとはイヤングゲンデ
    インダにより接続されてなる集積回路。
JP58101317A 1983-06-07 1983-06-07 集積回路パツケ−ジ Pending JPS59227143A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58101317A JPS59227143A (ja) 1983-06-07 1983-06-07 集積回路パツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58101317A JPS59227143A (ja) 1983-06-07 1983-06-07 集積回路パツケ−ジ

Publications (1)

Publication Number Publication Date
JPS59227143A true JPS59227143A (ja) 1984-12-20

Family

ID=14297431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58101317A Pending JPS59227143A (ja) 1983-06-07 1983-06-07 集積回路パツケ−ジ

Country Status (1)

Country Link
JP (1) JPS59227143A (ja)

Cited By (89)

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JPS61128548A (ja) * 1984-11-27 1986-06-16 Matsushita Electronics Corp 半導体装置
JPH0774277A (ja) * 1994-07-11 1995-03-17 Matsushita Electron Corp 半導体装置
JP2519332B2 (ja) * 1988-07-08 1996-07-31 沖電気工業株式会社 半導体装置
JPH0997868A (ja) * 1995-09-28 1997-04-08 Dainippon Printing Co Ltd リードフレーム部材及びその製造方法
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