JPS5957344A - レジスタ制御方式 - Google Patents

レジスタ制御方式

Info

Publication number
JPS5957344A
JPS5957344A JP57145961A JP14596182A JPS5957344A JP S5957344 A JPS5957344 A JP S5957344A JP 57145961 A JP57145961 A JP 57145961A JP 14596182 A JP14596182 A JP 14596182A JP S5957344 A JPS5957344 A JP S5957344A
Authority
JP
Japan
Prior art keywords
register
multiplier
load
sign bit
input operand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57145961A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6235691B2 (2
Inventor
Hideo Miyanaga
宮永 秀雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57145961A priority Critical patent/JPS5957344A/ja
Publication of JPS5957344A publication Critical patent/JPS5957344A/ja
Publication of JPS6235691B2 publication Critical patent/JPS6235691B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49994Sign extension

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Executing Machine-Instructions (AREA)
JP57145961A 1982-08-23 1982-08-23 レジスタ制御方式 Granted JPS5957344A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57145961A JPS5957344A (ja) 1982-08-23 1982-08-23 レジスタ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57145961A JPS5957344A (ja) 1982-08-23 1982-08-23 レジスタ制御方式

Publications (2)

Publication Number Publication Date
JPS5957344A true JPS5957344A (ja) 1984-04-02
JPS6235691B2 JPS6235691B2 (2) 1987-08-03

Family

ID=15397016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57145961A Granted JPS5957344A (ja) 1982-08-23 1982-08-23 レジスタ制御方式

Country Status (1)

Country Link
JP (1) JPS5957344A (2)

Also Published As

Publication number Publication date
JPS6235691B2 (2) 1987-08-03

Similar Documents

Publication Publication Date Title
US4953119A (en) Multiplier circuit with selectively interconnected pipelined multipliers for selectively multiplication of fixed and floating point numbers
EP0049039A1 (en) Data processing apparatus for processing sparse vectors
US3202805A (en) Simultaneous digital multiply-add, multiply-subtract circuit
JPS63160406A (ja) 非巡回型有限インパルス応答デジタルフィルタ
US4939684A (en) Simplified processor for digital filter applications
JPH0267691A (ja) 画像処理用集積回路
JPS62251843A (ja) 論理シミユレ−シヨン方法および装置
JPS5957344A (ja) レジスタ制御方式
JPS58182758A (ja) 演算制御装置
Zeman et al. A high-speed microprogrammable digital signal processor employing distributed arithmetic
JPS5968058A (ja) フロ−テイング乗算器
US3400259A (en) Multifunction adder including multistage carry chain register with conditioning means
US5650952A (en) Circuit arrangement for forming the sum of products
JPH04314209A (ja) ディジタルビット直列信号処理のための回路装置
JPS59106043A (ja) パイプライン演算回路
JP2696903B2 (ja) 数値計算装置
JPS6353572B2 (2)
JPH03129523A (ja) データ処理方法及び装置
GB2037040A (en) Numerical control of machines
JPS6083176A (ja) ベクトルプロセツサ
JPS58213354A (ja) パイプライン制御情報処理装置
JP2567985B2 (ja) ディジタル回路のパス自動選択方法及びディジタル回路のパス自動選択装置
JPS5578356A (en) Error information check method of card information processing unit and its circuit
JPS6072068A (ja) デイジタル高速相関器
JPS62297938A (ja) マイクロプログラム制御装置