JPS5996852U - 半導体装置用パツケ−ジ - Google Patents

半導体装置用パツケ−ジ

Info

Publication number
JPS5996852U
JPS5996852U JP1982192663U JP19266382U JPS5996852U JP S5996852 U JPS5996852 U JP S5996852U JP 1982192663 U JP1982192663 U JP 1982192663U JP 19266382 U JP19266382 U JP 19266382U JP S5996852 U JPS5996852 U JP S5996852U
Authority
JP
Japan
Prior art keywords
recess
conductor layer
packages
projection
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982192663U
Other languages
English (en)
Inventor
松尾　常樹
Original Assignee
九州日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 九州日本電気株式会社 filed Critical 九州日本電気株式会社
Priority to JP1982192663U priority Critical patent/JPS5996852U/ja
Publication of JPS5996852U publication Critical patent/JPS5996852U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図ａ、　　ｂは従来のサーディンプ型パッケージの
一例の平面図及び断面図、第２図は本考案の一実施例の
断面図である。 １．１１・・・・・・容器、２．１２・・・・・・凹部
、３゜１３・・・・・・導体層、４，１４・・・・・・
リード、５，１５・・・・・・ガラス、６．１６・・・
・・・半導体チップ、７．８・・・・・・金属細線、９
・・・・・・サブチップ、１９・・・・・・凸部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 絶縁体で作られ上部中央部に半導体チップを搭載する凹
    部を有する容器と、前記凹部内に前記搭載されるべき半
    導体チップと間隔をおくように設けられ、かつ前記容器
    上面よりも低くなる高さを有する凸部と、前記凹部底面
    と前記凸部上面上を覆う導体層と、前記凸部側面に設け
    られ前記凹部底面導体層と凸部上面導体層とを電気的に
    接続する導体層と、前記容器に設けられた外部引出し７
    用リードとを含むことを特徴とする半導体装置用パッケ
    ージ。
JP1982192663U 1982-12-20 1982-12-20 半導体装置用パツケ−ジ Pending JPS5996852U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982192663U JPS5996852U (ja) 1982-12-20 1982-12-20 半導体装置用パツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982192663U JPS5996852U (ja) 1982-12-20 1982-12-20 半導体装置用パツケ−ジ

Publications (1)

Publication Number Publication Date
JPS5996852U true JPS5996852U (ja) 1984-06-30

Family

ID=30414568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982192663U Pending JPS5996852U (ja) 1982-12-20 1982-12-20 半導体装置用パツケ−ジ

Country Status (1)

Country Link
JP (1) JPS5996852U (ja)

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