JPS60187536U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS60187536U
JPS60187536U JP1984074726U JP7472684U JPS60187536U JP S60187536 U JPS60187536 U JP S60187536U JP 1984074726 U JP1984074726 U JP 1984074726U JP 7472684 U JP7472684 U JP 7472684U JP S60187536 U JPS60187536 U JP S60187536U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
substrate
semiconductor pellet
semiconductor
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984074726U
Other languages
English (en)
Inventor
慎一 鈴木
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP1984074726U priority Critical patent/JPS60187536U/ja
Publication of JPS60187536U publication Critical patent/JPS60187536U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/011—Apparatus therefor
    • H10W72/0113—Apparatus for manufacturing die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示す要部平面図、第２図は
第１図の半導体装置の製造途中でのリードフレームの部
分平面図、第３図及び第４図は第２図のＣ−Ｃ線に沿う
各状態での断面図、゛第５図は本考案の他の実施例を示
す半導体装置の製造途中でのリードフレームの部分平面
図、第６図及び第７図は従来の半導体装置の要部平面図
及びＡ−Ａ線に沿う断面図、第８図は第６図の半導体装
置の等価回路図、第９図は第６図の半導体装置製造に使
用するリードフレームの部分平面図、第１０図は第９図
のリードフレームの製造途中の部分拡大図、第１１図及
び第１２図は第１０図のＢ−Ｂ線に沿う各状態での断面
図を示す。 ４、・・・・・・半導体ペレットマウント部、４′・・
・・・・エツジ、７・・・・・・半導体ペレット、１０
・・・・・・半田、１１′・・・・・・エツジ。 よ＃ａ−（ ＴＴ Ｊ＋（λも　　　　　。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基板の半導体ペレットマウント部上に半田を介して半導
    体ペレットをマウントしたものにおいて、前記半導体ペ
    レットマウント部を基板側壁近傍に位置させ半田の一部
    を基板側壁と隣接部分に食み出させたことを特徴とする
    半導体装置。
JP1984074726U 1984-05-21 1984-05-21 半導体装置 Pending JPS60187536U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984074726U JPS60187536U (ja) 1984-05-21 1984-05-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984074726U JPS60187536U (ja) 1984-05-21 1984-05-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS60187536U true JPS60187536U (ja) 1985-12-12

Family

ID=30615282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984074726U Pending JPS60187536U (ja) 1984-05-21 1984-05-21 半導体装置

Country Status (1)

Country Link
JP (1) JPS60187536U (ja)

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