JPS6020143U - Ｌｓｉチツプ - Google Patents

Ｌｓｉチツプ

Info

Publication number
JPS6020143U
JPS6020143U JP1983112083U JP11208383U JPS6020143U JP S6020143 U JPS6020143 U JP S6020143U JP 1983112083 U JP1983112083 U JP 1983112083U JP 11208383 U JP11208383 U JP 11208383U JP S6020143 U JPS6020143 U JP S6020143U
Authority
JP
Japan
Prior art keywords
lsi chip
bumps
pads
recorded
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983112083U
Other languages
English (en)
Inventor
徹 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1983112083U priority Critical patent/JPS6020143U/ja
Publication of JPS6020143U publication Critical patent/JPS6020143U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案のＬＳＩチップを示す図、第２図イｔ　
　Ｏｔ　ハは同バンプの形成方法を説明する図である。 １はＬＳＩチップ、２は絶縁層、３はパッド、４はトリ
メタル、５はバンプ、６はマスク。

Claims (1)

    【実用新案登録請求の範囲】
  1. 複数個のパッドにそれぞれ一定サイズのバンプを形成し
    て成るＬＳＩチップに於て、前記バンプを適宜パッドの
    一部分にのみ結合するように位置をずらして形成してな
    ることを特徴とするＬＳＩチップ。
JP1983112083U 1983-07-18 1983-07-18 Ｌｓｉチツプ Pending JPS6020143U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983112083U JPS6020143U (ja) 1983-07-18 1983-07-18 Ｌｓｉチツプ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983112083U JPS6020143U (ja) 1983-07-18 1983-07-18 Ｌｓｉチツプ

Publications (1)

Publication Number Publication Date
JPS6020143U true JPS6020143U (ja) 1985-02-12

Family

ID=30259967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983112083U Pending JPS6020143U (ja) 1983-07-18 1983-07-18 Ｌｓｉチツプ

Country Status (1)

Country Link
JP (1) JPS6020143U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005265750A (ja) * 2004-03-22 2005-09-29 Elpida Memory Inc プローブカード
JP2013519227A (ja) * 2010-02-03 2013-05-23 ポリマー・ビジョン・ベー・フェー 多様な集積回路チップバンプピッチを有する半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005265750A (ja) * 2004-03-22 2005-09-29 Elpida Memory Inc プローブカード
JP2013519227A (ja) * 2010-02-03 2013-05-23 ポリマー・ビジョン・ベー・フェー 多様な集積回路チップバンプピッチを有する半導体装置

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