JPS60235253A - Trouble processing system - Google Patents

Abstract

PURPOSE:To gather trouble information of a main storage device by using a central processing unit to gather trouble information of the main storage device by a service processor if a trouble occurs in the main storage device. CONSTITUTION:When a gathering request of trouble information of a main storage device 1 is sent from a service processor 2, a microprogram is branched to an interruption processing routine at the instruction end time and sets trouble information from the main storage device 1 to a read register 10 and stores it in a buffer memory 11 thereafter. Since the microprogram requests the processor 2 to read contents of the memory 11 after this storage, an FF13 is set, and the microprogram is stopped, and trouble information of the memory 11 is read out to the processor 2. After read, a control signal which resets the FF13 is sent from the processor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a fault handling method for collecting fault information, and more particularly to a method for collecting fault information of a main storage device using a central processing unit.

(Prior Art) Conventionally, when a failure occurs inside a main storage device during data transfer from a channel, it has not been possible to collect failure information by a service processor. Therefore, if a failure occurs inside the main storage device during data transfer from the channel, there is a drawback in that it is impossible to collect information about the failure.

(Objective of the Invention) An object of the present invention is to notify the service processor of the occurrence of the fault when a fault occurs within the main memory [δ], and the service processor uses the central processing unit to restore the main memory The above drawbacks are resolved by collecting fault information, and the service processor is configured to be able to collect fault information even if a fault occurs inside the main storage device during data transfer from a channel. There are many ways to provide troubleshooting operations.

(Structure of the Invention) The failure handling method according to the present invention includes a request means, a first flip-flop, a microprogram control means, a buffer memory, a second 7-lip-flop, an execution stop means, and a reset fa control means. This was realized by configuring the system to include the following.

The request means is for requesting the service processor to handle the failure when a failure occurs in the main storage device.

The first flip-flop instructs Tatoki to read fault information from the main memory from the service processor when the above request occurs.

The microprogram control means performs interrupt processing at the end of instruction execution when the first flip-flop is set, reads all fault information from the main memory, and after reading the fault information, controls the first flip-flop. This is for resetting.

The buffer memory is for storing fault information.

The second flip-flop can be set by microprogram control to request the service processor to read the fault information stored inside the buffer memory.

The execution stop means is for stopping the execution of the microprogram by setting all the second flip-flops.

The reset control means is for causing the service processor to read the contents of the buffer memory in the stopped state, and for causing the service processor to reset the second flip-flop after reading.

(Example) Next, the present invention will be described in detail with reference to page 1.

Referring to FIG. 1, one embodiment of the fault handling method according to the present invention is realized by a central processing module m:3K connected to a main storage device 1 and a service processor 2. If a failure occurs in the service processor 1, the service processor 2 is notified of the occurrence of the failure via the signal line 100. In FIG. 1, 4 is a first decoding circuit;
5 is the first 7 lip flop, 6 is the address register,
7 is control memory, 8ke! fjll rn storage register, 9
1 is a branch control circuit, 10 is a read register, 11 is a buffer memory, 12 is a second decoding circuit, and 16 is a @2 flip-flop.

In District 1, the service processor 2
0j1] A request is made to the central processing unit 6 via the control signal line '101 to report the failure 1h of the main storage device 1. The control signal on the signal line 101 is decoded by the first decode circuit 4 and sets the first seven lip-flop 5 via the control signal line 102.

The central processing unit 3 sets the software operation code passed through the control signal line 103 in the address register 6 of the control memory, branches the operation code in the control memory 7, and sets the microprogram in the control memory register 8. The next microprogram completely determines the address of the control memory 7 through the signal line 104 according to some fields of the control memory register 8. The branching of the microprogram is performed by the output signal cross 4 of the branch control circuit 9, which receives the signal line 105 and the two-branch information signal line 106, which lead to some fields of the control storage register 8, as the input signal line 1.
Perform on 07.

When the service processor 2 sends out a request to collect failure information of the main storage device 1, the microprogram branches to an interrupt processing routine in response to a control signal on the signal line 108 at the end of the instruction. In the processing routine, a failure notification from the main storage device 1 is sent to the signal 19i! 10
9 and control signal line 110 to set it in the read register 10. Thereafter, the set 'f'A information is stored in the buffer memory 11 through the first gauze 111. After the storage is completed, the microprogram is 1 ill master signal m
The second decoding circuit 12 sends a reset signal onto the signal line 116 via the decoding circuit 112f to reset the first 7-lip-flop 5. In order to request the service processor 2 to read the contents of the buffer memory 11, the microprogram sends the set a signal to the signal line 11 through the second decoding circuit 12 via the control signal line 112' (i-).
4J2 and set the second 7 lip-flop 16. completion of the second flip-flop 13)(
-V inhibits updating of the flf control storage register 8 through a signal line 115, and requests reading from the service processor 2 through a request signal sent to the service processor 2 through a signal line 116.

While the second flip-flop 16 is set 2', the microprogram is stopped. During the above-mentioned stop period, fault information in the buffer memory 11 is read out to the service processor 2 using the signal line 118. After the reading is completed, a control signal is sent from the service processor 2 to the signal line 117 via the control signal line 101 to instruct the first decode circuit 4 to reset the second 7-resobflop 13. By resetting the second flip-flop 12, the microprogram is set in the control storage register 8 and execution is resumed. In this way, the first 7-lip flop 5 is used to instruct the main memory 1 to store fault information, and the second 7-lip flop 13 is used to request the service processor 2 to read the contents of the buffer memory 11. .

(Effects of the Invention) As described above, the present invention has a structure in which failure information in the main storage device when accessing a channel is stored in a service processor, which is useful for improving resolution when detecting a failure. But it has an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a configuration for realizing a failure handling method according to the present invention. 1...Main memory device 2...ΦService processor 3...Central processing unit 4.12/Fist/decode circuit 5.13...Flip-flop 61111 @Address register 7/Fist/control memory 8...Control kl: storage register 9...branch control circuit 10...read register 110.・Buffer memory 100 to 118...Signal line patent applicant Nippon Densho Co., Ltd. agent Patent attorney Inoro Masu

Claims (1)

[Scope of Claims] Request means for requesting a service processor to completely process the failure when a failure occurs in the main storage, and information on the failure of the main storage from the service processor when the request occurs. A first flip-flop for instructing to read the above, and an interrupt processing at the end of instruction execution when the first Noritsubu flop is set, read all fault information in the main memory, a microprogram control means for resetting the first seven lip flops after reading fault information; a buffer memory for storing the fault information; and a reading system for the fault information stored in the backup memory. a second seven-lip flop, which can be set by the microprogram control means to request the service processor to perform the following steps: execution stopping means for stopping the execution of the microprogram by setting the second flip-flop; reading the contents of the buffer memory by the service processor in the stopped state; 2. A failure handling method characterized in that the fault handling method is realized by comprising: a reset control means for resetting the second seven-lip flop;