JPS6030539U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6030539U
JPS6030539U JP1983123362U JP12336283U JPS6030539U JP S6030539 U JPS6030539 U JP S6030539U JP 1983123362 U JP1983123362 U JP 1983123362U JP 12336283 U JP12336283 U JP 12336283U JP S6030539 U JPS6030539 U JP S6030539U
Authority
JP
Japan
Prior art keywords
terminals
semiconductor equipment
electrodes
substrate
longitudinal direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983123362U
Other languages
English (en)
Inventor
仁平　一也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP1983123362U priority Critical patent/JPS6030539U/ja
Publication of JPS6030539U publication Critical patent/JPS6030539U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図はダーリントントランジスタの回路図、第２図は
従来の２並列ダーリントントランジスタの平面図、第３
図は本考案の一実施例の平面図である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基板上に固定された半導体チップの一表面上の複数の電
    極が同様に前記基板上に固定される三つ以上の外部引出
    し端子のいずれかとそれぞれ導線によって接続されるも
    のにおいて、外部引出し端子がその長手方向を半導体チ
    ップめ対向する両辺に平行に位置し、チップ上の電極と
    の接続導線が前記端子の長手方向にほぼ直角に位置する
    ことを特徴とする半導体装置。
JP1983123362U 1983-08-09 1983-08-09 半導体装置 Pending JPS6030539U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983123362U JPS6030539U (ja) 1983-08-09 1983-08-09 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983123362U JPS6030539U (ja) 1983-08-09 1983-08-09 半導体装置

Publications (1)

Publication Number Publication Date
JPS6030539U true JPS6030539U (ja) 1985-03-01

Family

ID=30281628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983123362U Pending JPS6030539U (ja) 1983-08-09 1983-08-09 半導体装置

Country Status (1)

Country Link
JP (1) JPS6030539U (ja)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028272A (ja) * 1973-07-11 1975-03-22
JPS5287363A (en) * 1976-01-17 1977-07-21 Nec Corp Semiconductor packdage
JPS54573A (en) * 1977-06-02 1979-01-05 Mitsubishi Electric Corp Transistor
JPS5664459A (en) * 1979-10-29 1981-06-01 Toshiba Corp Transistor amplifier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028272A (ja) * 1973-07-11 1975-03-22
JPS5287363A (en) * 1976-01-17 1977-07-21 Nec Corp Semiconductor packdage
JPS54573A (en) * 1977-06-02 1979-01-05 Mitsubishi Electric Corp Transistor
JPS5664459A (en) * 1979-10-29 1981-06-01 Toshiba Corp Transistor amplifier

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