JPS603161A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the dielectric resistance of a P-N junction by forming a polycrystalline Si layer containing a P type impurity while crossing the surface exposed section of the P-N junction and coating the whole surface containing the polycrystalline Si layer with an insulating film when a P type region is diffused and shaped to the surface layer section of an N type semiconductor substrate and a semiconductor device with the P-N junction is manufactured. CONSTITUTION:A P type region 2 is diffused and formed to the surface layer section of an N type Si substrate 1 and a P-N junction is shaped, a P type polycrystalline Si layer 5 of a predetermined shaped is formed on the substrate 1 while crossing the surface exposed section of the P-N junction, and the whole surface containing the polycrystalline Si layer is coated with an insulating film 3. Consequently, the surface of the substrate 1 under the layer 5 is changed into P type, a depletion layer from the region 2 is easy to expand to the section C and the dielectric strength of the junction is increased. Impurities from the outside are difficult to intrude to the substrate 1 by the presence of the layer 5, and the reliability of a device is improved. The area of an element is reduced because the size of the layer 5 may be small.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a PN junction. Conventionally, as a means of increasing the withstand voltage of a semiconductor device including a PN junction, as shown in FIG. Gold manuscripts that have contact with area 2 (e.g. A-
13) 4 is formed via an insulator 3 (hereinafter referred to as a field plate) to weaken the electric field strength at the C portion under the metal 4. However, the field-plate is r
Since the electric field intensity is weakened through the oxidized film 3, it is affected by the thickness of the oxidized film 3, i91, and the effect becomes unstable. Also,
Since the area for contact with the impurity region 2 and the length of the gold plate 4 as a field plate are required, a large area is required, and this is not suitable for miniaturization of the device.

An object of the present invention is to obtain a semiconductor device suitable for miniaturization that has a PN junction with stable characteristics and high breakdown voltage.

The present invention uses a thermal oxide film and a photolithography technique to form a metal of the opposite conductivity type on a semiconductor substrate having a -conductivity type. An impurity region is formed, and a polycrystalline silicon layer having a conductivity type opposite to that of the semiconductor substrate is directly applied to the semiconductor substrate so as to straddle the PN junction formed by the semiconductor substrate and the impurity region, or slightly away from the PN junction. It is characterized by being formed on a substrate.

A polycrystalline silicon layer having a tL type of conductivity opposite to that of the semiconductor substrate is formed in the vicinity of a PN junction formed by the semiconductor substrate and an impurity region having an opposite conductivity type. Therefore, the impurity concentration on the surface of the semiconductor substrate under this polycrystalline silicon layer is small, υ, and the depletion layer from the impurity region easily spreads on the surface of the semiconductor substrate under the polycrystalline silicon layer, making it possible to increase the breakdown voltage. can.

Next, the present invention will be explained using examples.

In FIG. 2, for example, the N-type semiconductor substrate 1 is
Create a P-type impurity region 2 using phosphorography technology,
PN formed by these semiconductor substrate 1 and impurity region 2
A polycrystalline silicon layer 5 containing a P-type impurity (for example, polycrystalline silicon containing several moles to several tens of moles of boron) is formed with gold so as to be in contact with the edges of the junction, and the entire surface is insulated. It is covered with 3. According to such a structure, the surface of the semiconductor substrate 1 under the polycrystalline silicon layer 5 becomes P, and a depletion layer from the impurity region 2 easily spreads to this portion C, and the PN between the semiconductor substrate 1 and the impurity region 2 increases. The breakdown voltage of the bond can be increased. In addition, 0 around impurity region 2
Since the portion is covered with the polycrystalline silicon layer 5, it is difficult for impurities from the outside to enter the semiconductor substrate 19, and reliability can be improved. Furthermore, polycrystalline silicon layer 5
is directly adhered to the semiconductor substrate 1, and the effect of the polycrystalline silicon layer 5 directly affects the surface of the semiconductor substrate 1. Therefore, even if the length of the polycrystalline silicon layer 5 is short, the effect is sufficient. This results in a reduction in the required area of the semiconductor device. FIG. 3 also shows an embodiment using the present invention.

In this embodiment, polycrystalline silicon layer 5 is formed directly on semiconductor substrate 1 at a distance from impurity region 2 . 0 on the surface of the semiconductor substrate 1 under this polycrystalline silicon layer 5.
The depletion layer from the impurity region 2 is easy to spread in the 61 part of the outer periphery of the impurity region 2, but the depletion layer is difficult to spread in the 61 part of the outer periphery of the impurity region 2. Therefore, the shared voltage of 61 parts increases. By kneading, it is possible to further improve the pressure resistance.

FIG. 4 shows an embodiment in which the present invention is applied to a semiconductor element having a guard ring 2'.
A P-shaped guard ring 2' is provided on the outer periphery of and surrounding h. When a high voltage is applied to the P-type head region 2, the depletion layer is connected to the depletion layer of the guard ring 2', increasing the withstand voltage. A P-type polycrystalline silicon layer 5.5' is formed on the semiconductor substrate on both sides of the guard link 2 in contact with it. Therefore, the depletion layer spreads easily in the C9C' portion below the polycrystalline silicon layer 5.5', making it possible to further improve the breakdown voltage.

In this way, by forming a polycrystalline silicon layer with a conductivity type opposite to that of the substrate in areas where it has been difficult for the depletion layer to spread, the concentration of the semiconductor substrate under the polycrystalline silicon layer can be lowered, and in this area, It makes it easier for the depletion layer to expand.

In addition, although we have added an explanation about the N-type semiconductor substrate,
It goes without saying that the present invention is similarly applicable to type semiconductor substrates.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional example. Figure 2. FIGS. 3 and 4 are sectional views showing embodiments of the present invention, respectively. 1... Semiconductor substrate, 2... Impurity region, 3... Insulator, 4... Field.
play), 5.5'...polycrystalline silicon layer, 2
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Claims (1)

[Claims] 1) - An impurity region having a different conductivity type is formed in a semiconductor substrate having a conductivity type, and the impurity region is formed in a PN junction formed by the semiconductor substrate and the impurity region or in the vicinity of the semiconductor substrate. A semiconductor device characterized in that a polycrystalline silicon layer having another conductivity type is formed. 2) The semiconductor device 1δ according to claim 1, wherein the polycrystalline silicon layer is formed in contact with the semiconductor substrate.