JPS61151764A - Ｉ／ｏデバイス制御装置 - Google Patents

Ｉ／ｏデバイス制御装置

Info

Publication number
JPS61151764A
JPS61151764A JP27287784A JP27287784A JPS61151764A JP S61151764 A JPS61151764 A JP S61151764A JP 27287784 A JP27287784 A JP 27287784A JP 27287784 A JP27287784 A JP 27287784A JP S61151764 A JPS61151764 A JP S61151764A
Authority
JP
Japan
Prior art keywords
control
channel
control unit
section
route
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27287784A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0410659B2 (2
Inventor
Moriji Sugimoto
杉本　守二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP27287784A priority Critical patent/JPS61151764A/ja
Publication of JPS61151764A publication Critical patent/JPS61151764A/ja
Publication of JPH0410659B2 publication Critical patent/JPH0410659B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP27287784A 1984-12-26 1984-12-26 Ｉ／ｏデバイス制御装置 Granted JPS61151764A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27287784A JPS61151764A (ja) 1984-12-26 1984-12-26 Ｉ／ｏデバイス制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27287784A JPS61151764A (ja) 1984-12-26 1984-12-26 Ｉ／ｏデバイス制御装置

Publications (2)

Publication Number Publication Date
JPS61151764A true JPS61151764A (ja) 1986-07-10
JPH0410659B2 JPH0410659B2 (2) 1992-02-26

Family

ID=17520005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27287784A Granted JPS61151764A (ja) 1984-12-26 1984-12-26 Ｉ／ｏデバイス制御装置

Country Status (1)

Country Link
JP (1) JPS61151764A (2)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111516A (ja) * 1982-12-17 1984-06-27 Fujitsu Ltd インタ−フエイス切り換え方式

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111516A (ja) * 1982-12-17 1984-06-27 Fujitsu Ltd インタ−フエイス切り換え方式

Also Published As

Publication number Publication date
JPH0410659B2 (2) 1992-02-26

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