JPH02218090A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To sense information read to a bit line at high sensitivity and at high speed by providing a highly sensitive sense amplifier with a pair of MOSFETs, which have prescribed gate lengths and are mutually crossly connected, and a pair of the MOSFETs, which have shorter gate lengths than the amplifiers and are mutually crossly connected. CONSTITUTION:Sense amplifiers 16 and 17 are both of a C-MOSFET type, and the gate lengths of constituting elements 19 to 22 of the highly sensitive sense amplifier 16 are long, and the elements 25 to 28 of the high-speed sense amplifier 17 are short. Consequently the turned-on resistances of the elements 19 to 22 are high, inflow and outflow currents of bit lines BL and the inverse of BL are gentle and the sense amplifier becomes highly sensitive at the time of a start of operation. The turned-on resistances of the elements 25 to 28 are low, the inflow and outflow currents of the bit lines are sharp, and the sense amplifier is made fast. The gates of FETs 23 and 24 are narrowed, and FETs 29 and 30 are broadened. In such a way, the sense amplifiers are respectively independently formed and optimized, and thus the sense amplifiers at high sensitivity and at high speed is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to semiconductor memory, particularly dynamic random access memory (D-RAM), and provides a method for reading selected memory cells with high sensitivity and high speed. This relates to the configuration of the sense amplifier.

(b) Conventional technology In general, in a folded bit line type D-RAM,
The memory cell selected by the word line is connected to the bit line, and the weak potential difference generated between the bit line pair is amplified by a flip-flop type sense amplifier and the signal is read out.

Figure 7 shows a conventional D-type circuit using such a sense amplifier.
It is a circuit diagram of RAM.

In the figure, a bit line pair BL on which a memory cell (1) is arranged, BL includes a sense amplifier (2), a MOS transistor for bit line equalization (3), and a MOS transistor for bit line precharge (4). (5) is connected.

The sense amplifier (2) includes an N-channel type MOS transistor (6) and a P-channel type MOS transistor connected in series.
Transistor (7), N-channel type MOS transistor (8) and P-channel type MO5 connected in series
I-transistor (9), and the gates and drains of each of the MOS transistors (6) and (7) connected in series and the gates and drains of the MOS transistors (8) and (9) are mutually connected to each other through 0s, The connection points thereof are connected as sense nodes to bit line pairs BL and BL, respectively.

In addition, the sources of the MOS transistors (6) and (8) are commonly connected, and the M
O3I - grounded via transistor (10), MOS
The sources of the transistors (7) and (9) are connected in common,
Sense control signal φ1. MO8I is connected to the voltage RV oo via a transistor (11) controlled by MO8I.

The MOS transistor (3) for bit line equalization is
The bit lines BL and BL are short-circuited to have the same potential, and are configured as an N-channel type, and a precharge signal≠2 is applied to the gate.

MOS transistor for bit line precharge <4) (
5) precharges the bit lines BL, BL to a constant voltage, for example, V Do/2 during standby, and is constructed of an N-channel type, and a precharge signal -1 can be applied to its gate.

Next, the operation of the circuit shown in FIG. 7 will be explained. While the row address control signal RASC1') is at "H" level, that is, during standby, the precharge signal φ
, is at “H” level, MOS transistor (3) (
4) According to (5), bits fiBL and BL are set to V that has been completely generated by a precharge voltage generation circuit (not shown).
It is held at o o/2. Also, sense amplifier
2), the common lines S8 and SP that drive Voo
/2 can ask for precharge.

When the row address control signal RAS falls to the "L" level, the precharge signal φ becomes the 1L" level, all MOS transistors (3), (4), and (5) are turned off, and bits MBL and BL are turned off. When one of the floating primary word lines WL becomes ``H'' level and the information of the memory cell (1) is read out to either the bit line BL or BL, the bit lines BL and BL A slight potential difference occurs between them.Then, the sense control signals φ and N become “H”.
When the sense control signal φ5. reaches the "L" level, the sensing operation of the sense amplifier (2) is started, and the potential difference between the bit lines BL and 11 is expanded.

The above-mentioned D-RAM is described in detail in Japanese Unexamined Patent Publication No. 140488/1988.

(c) Problems to be Solved by the Invention In recent years, as D-RAMs have increased in capacity, memory cells have become smaller and more highly integrated. Such a large capacity D-
RAM requires a highly sensitive sense amplifier to accurately read data from small memory cells.

However, in order to make the sense amplifier shown in FIG. 7 highly sensitive, the channel length GL of the MOS transistors (6) (7) (8) (9) constituting the sense amplifier (2) must be increased.
Lengthen MO9I-transistor (6) (7) (8) (
It is necessary to align the characteristics of 9). However, there is a problem that increasing the channel length GL lowers the sensing speed.

(d) Means for solving the problems The present invention was created in view of the above points,
A pair of M having a predetermined gate length and cross-connected to each other
It is equipped with a high-sensitivity sense amplifier having an OS transistor, and a high-speed sense amplifier including a pair of MOS transistors having a gate length shorter than the gate length of an MO5 transistor of the high-sensitivity sense amplifier and connected to each other through terminals. The purpose of this is to sense the information of the memory cell read to the bit line with high sensitivity and at high speed.

(f) Function According to the above-mentioned means, after the potential difference based on the information of the memory cell read to the bit line is sense-amplified by the high-sensitivity sense amplifier, the potential difference can be rapidly expanded by the high-speed sense amplifier. Become.

In addition, by directly connecting the bit line and the high-speed sense amplifier, and by providing a separation transistor between the high-speed sense amplifier and the high-sensitivity sense amplifier, the bit line capacitance unbalance seen from the high-sensitivity sense amplifier can be sensed. It is possible to reduce the impact on

Furthermore, by directly connecting the bit line and the high-sensitivity sense amplifier, and by providing a separation transistor between the high-sensitivity sense amplifier and the high-speed sense amplifier, after the high-sensitivity sense amplifier operates, the isolation transistor separates the two, allowing the high-speed sense amplifier to operate. The sensing results of the high-speed sense amplifier can be accessed at high speed using column address data.

(f) Embodiment FIG. 1 does not show an embodiment of the present invention, but is a circuit diagram of a D-RAM.

Dynamic memory cells (12) are alternately connected to the intersections of a pair of bit lines BL, BL and word lines WL, ~WLn, and N-channel MO8I-transistors (12) for precharging are connected to bit lines BL, BL. 13>(14)
and an N-channel MOS transistor for equalization (1
5) is connected, as well as a high-sensitivity sense amplifier (16L high-speed sense amplifier (17)) and a selection MOS transistor (18) selected by the column line CLn.

The MOS transistors (13) (L4) (15) are controlled by a precharge signal d, and in the standby state, the MOS transistors (13) (14>) precharge the bit lines BL, BL with a precharge voltage v p (this implementation In the example, it is precharged to 1/2 of the power supply voltage V0),
The MOS transistor (15) short-circuits the bit lines BL and BL to equalize the potential.

The high-sensitivity sense amplifier (16) is a C-MO37 lip-prop type consisting of N-channel MOS transistors (19) (20) and P-channel MOS transistors (21) (22) whose gates and drains are cross-connected to each other. It is a sense amplifier of MOS transistor (
19) Source of (20) and MOS transistor (21)
The sources of (22) are the sense amplifier drive line S N
t and SP. sense amplifier drive line SN,
is grounded by an N-channel MOS transistor (23) controlled by a sense control signal φssl,
Sense amplifier drive line SP, sense control signal φsp+
P-channel MOS transistor (
24) t′tA voltage V. , is connected to. Furthermore, in the standby state, the sense amplifier drive lines S P r and SNI are precharged to the precharge voltage VP similarly to the bit lines BL and BL.

On the other hand, the high-speed sense amplifier (17) is an N-channel MOS transistor (similar to the high-sensitivity sense amplifier (16)).
25) (26) and P-channel MO5 transistor (2
7) (28), MOS transistor (25)
(26) (7) 7-s and MoS transistor (27
) (2B) The no sources are sense amplifier drive BS and N, respectively.
, and SP. Sense amplifier drive lines SN and SP receive sense control signals -6□ and 6. are respectively connected to MOS transistors (29) and (30) controlled by □,
In the standby state, the precharge voltage V,
is precharged.

This high sensitivity sense amplifier (16) and high speed sense amplifier <
The difference in 17) lies in the MOS transistors that constitute it.

That is, the gate length GL of the MOS transistors (19), (20), (21), and (22) constituting the high-sensitivity sense amplifier (16) is long, and the gate length GL of the MOS transistor (25) constituting the high-speed sense amplifier (17) is long. (26) (27)
The gate length GL of (28) is formed short. Specifically, in this example, the Mo3 transistor (19) (
20) The gate length GL of (21) and (22) is 2.0μrn
MOS transistor (25) (25)
(27) The gate length GL of (28>) is formed to be about 1.2 μm. Therefore, the on-resistance of the Mo5 transistor (19) (20) (21) (22) with a long gate length GL becomes high. At the start of operation, the 11L current flowing into the bit lines BL and BL and the current flowing out become gentle, and the sense amplifier (16) becomes highly sensitive. In addition, MOS transistors (25) (26) (27) (2,8
) becomes smaller, so the current flowing into and out of the bit lines BL and BL becomes rapid at the start of operation.
The sense amplifier (17) becomes high speed.

Furthermore, the gate width GW of the MOS transistors (23) and (24) is narrow, and the MoS transistors 2. Evening (29) (3
0)+7) The gate width GW is formed wide.

Next, the operation timing of the circuit shown in FIG. 1 will be explained with reference to FIG. 2.

First, when the column address control signal RAS falls to the "L" level, the precharge signal φP goes to the "L" level.As a result, the bit lines BL, BL are precharged to the voltage VP. Then, based on the row address data, the word lines WL,
~ When any one of WLrh becomes "H" level, the memory cell (12) is connected to one of the bit lines BL and BL, and the bit line that was balanced by the charge accumulated in the memory cell (12) A potential difference occurs between BL and BL. Then, the sense control signal -IPI and φIH1 are simultaneously low.
When the level reaches the "H" level, the Mo8 +- transistors (24) and (23) turn on, and the high-sensitivity sense amplifier (1
6) sensing operation is started. High sensitivity sense amplifier (
16> sense operation progresses to some extent, and the bit lines BL and B
At the point when the potential difference between L gradually increases, the sense control signal φ
S□ and iSl become "L II level" and "H" level. As a result, the MOS transistors (30) and (29) are turned on, the high-speed sense amplifier (17) starts operating, and the potential difference between the bit lines BL and BL rapidly increases.

With the above operations, reading of information stored in the memory cell (12) is completed.

FIG. 3 is a circuit diagram showing another embodiment of the present invention, in which the same parts as in FIG. 1 are given the same reference numerals. 17) is directly connected, and the high-sensitivity sense amplifier (16) is connected to the isolation MO
A high-speed sense amplifier (1) is connected via an S transistor (31).
7) and the bit lines BL, BL.

Mo8) The transistor (31) is controlled by the timing signal -1, but a fixed potential may be applied to the gate to keep the MOS transistor (31) always on.

The operation timing when the Mo5h transistor (31) is always on is exactly the same as in FIG. 2. In this case, the MOS transistor (31) acts as a resistor,
Bit lines BL and B seen from high sensitivity sense amplifier (16)
This prevents the unbalance of the capacitance of L from causing a decrease in the sensitivity of the sensing operation. That is, if there is a capacitance imbalance between the bit lines BL and BL, the bit lines BL and BL during sensing operation
Voltage changes caused by charging and discharging the BL become unbalanced, but since the MOS transistor (31) serves as a resistor, this unbalance is less likely to be transmitted to the high-sensitivity sense amplifier (16).

When the MOS transistor (31) is controlled by the timing signal φi, the timing is as shown in FIG. All timings in FIG. 4 are the same as those in FIG. 2 except for Ji. The timing signal φi is applied to the bit line BL when one of the word lines WL, -WLn becomes 'H' level.

After a potential difference is generated in BL and before the high-sensitivity sense amplifier (16) starts operating by the sense control signal φSFI and φ3, 11, it becomes “L I+ level. Therefore,
The high-sensitivity sense amplifier (16) performs a sensing operation in a state where the MOS transistor (31) is turned off and is separated from the high-speed sense amplifier (17) and the bit lines BL and EL. As a result, the sensing operation of the high-sensitivity sense amplifier (16) becomes a highly sensitive sensing operation without being affected by the capacitance imbalance between the bit lines BL and BL. Then, as the sense operation progresses by a certain degree, the potential difference at the sense input terminal of the high 14 degree sense amplifier (16) expands.
The timing signal≠i becomes "H" 1 level and the MOS transistor (31) is turned on, and the sense control signal≠S□.

-□ starts the operation of the high-speed sense amplifier (17). As a result, the potential difference between the bit lines BL and B rapidly increases.

FIG. 5 is a circuit diagram showing still another example of the present invention,
The same parts as in FIG. 1 are given the same reference numerals.

The difference from Fig. 1 is that the bit lines BL and B connecting the high-sensitivity sense amplifier (16) and the high-speed sense amplifier (17)
N-channel MO controlled by timing signal φj
This is because an S transistor (32) is provided. This embodiment speeds up column address access by separating the high-speed sense amplifier (17).

That is, as shown in the timing diagram of FIG. 6, when the sensing operation of the high-sensitivity sense amplifier (16) has progressed to a certain extent and the potential difference between bits 1IiBL and BL has expanded, the timing signal ≠j is set to ``L'' level. MOS)-runsistor (32) is turned off, and the sense control signal≠1□
, φ1□ causes the high-speed sense amplifier (17) to start operating. This allows high-speed sense amplifier (17)
can be freed from the capacitive load of the bit lines BL and BL, and can perform faster sensing operations. Therefore, the high-speed sense amplifier (
As soon as the operation 17) is completed -γ, one column line CLn based on the column address data is set to the "H+t level" and the read signal can be taken out to the human output line I10.I10. That is, This allows for fast column access.

On the other hand, the separated high-sensitivity sense amplifier (16) continues to operate, and eventually completes the sensing operation, although it takes time, and increases the potential difference between the bit lines BL and BLf to the maximum.

(G) Effects of the Invention As described above, according to the present invention, by providing a high-sensitivity sense amplifier and a high-speed sense amplifier independently, it becomes possible to optimize each sense amplifier separately, thereby achieving high sensitivity and high speed. sense amplifier circuit can be realized. Further, by providing a separation transistor between the high-speed sense amplifier and the high-sensitivity sense amplifier, it is possible to prevent a decrease in sense sensitivity due to unbalanced bit line capacitance. Furthermore, by independently operating the high-speed sense amplifiers, column access time can be shortened.

In addition, even when a separate MOS transistor is provided, since either one of the sense amplifiers is connected to the bit line, the voltage transmitted to the bit line is reduced by the threshold voltage, unlike the conventional separated MOS transistor. There is also the advantage that there is no need to apply a voltage higher than the XSt pressure to the gate in order to prevent C.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing another embodiment of the invention. 4 is a timing diagram showing the operation of the circuit shown in FIG. 3, FIG. 5 is a circuit diagram showing another embodiment, and FIG. 6 is a timing diagram showing the operation of the circuit shown in FIG. 5. , FIG. 7 is a circuit diagram showing a conventional example. (12)...Memory cell, (16)...High sensitivity sense amplifier, (17)...High speed sense amplifier.

Claims (3)

[Claims] (1) A plurality of word lines, a plurality of bit line pairs, a memory cell arranged between the word line and the bit line pair, and a sense amplifier section each connected to the bit line pair. In the semiconductor memory, the sense amplifier section has a high-sensitivity sense amplifier including a pair of MOS transistors that have a predetermined gate length and are cross-connected to each other, and a gate length that is shorter than the gate length of the MOS transistor of the high-sensitivity sense amplifier. A semiconductor memory comprising a high-speed sense amplifier including a pair of MOS transistors cross-connected to each other. (2) The semiconductor memory according to claim 1, wherein a separation MOS transistor is connected between the high-sensitivity sense amplifier and the high-speed sense amplifier to electrically isolate them from each other. (3) A pair of sense nodes of the high-sensitivity sense amplifier are directly connected to the bit line pair, and a pair of sense nodes of the high-speed sense amplifier are connected to the bit line pair via the separation MOS transistor, and 2. The semiconductor memory according to claim 1, wherein a selection transistor selected by a column address is connected between the sense node of the high-speed sense amplifier and the common input/output line.