JPS6199997A - 併合型不揮発性メモリセルマトリツクの書込み方法 - Google Patents

併合型不揮発性メモリセルマトリツクの書込み方法

Info

Publication number: JPS6199997A
Authority: JP; Japan
Prior art keywords: voltage; gate; drain; cells; cell
Prior art date: 1984-10-23
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Pending

Application number

JP60234659A

Other languages

English (en)

Japanese (ja)

Inventor

アンドレア・ラバグリア

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

S JI S MIKUROERETSUTORONIKA SP

S JI S MIKUROERETSUTORONIKA SpA

Original Assignee

S JI S MIKUROERETSUTORONIKA SP

S JI S MIKUROERETSUTORONIKA SpA

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1984-10-23

Filing date

1985-10-22

Publication date

1986-05-19

1985-10-22 Application filed by S JI S MIKUROERETSUTORONIKA SP, S JI S MIKUROERETSUTORONIKA SpA filed Critical S JI S MIKUROERETSUTORONIKA SP

1986-05-19 Publication of JPS6199997A publication Critical patent/JPS6199997A/ja

Status Pending legal-status Critical Current

Links

239000011159 matrix material Substances 0.000 title description 11
238000000034 method Methods 0.000 claims description 7
239000000758 substrate Substances 0.000 description 4
XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
229910052710 silicon Inorganic materials 0.000 description 3
239000010703 silicon Substances 0.000 description 3
230000000694 effects Effects 0.000 description 2
230000002939 deleterious effect Effects 0.000 description 1
238000010586 diagram Methods 0.000 description 1
238000007599 discharging Methods 0.000 description 1
230000005684 electric field Effects 0.000 description 1
238000004519 manufacturing process Methods 0.000 description 1
229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
230000010287 polarization Effects 0.000 description 1
229910021420 polycrystalline silicon Inorganic materials 0.000 description 1

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Read Only Memory (AREA)
Non-Volatile Memory (AREA)

JP60234659A 1984-10-23 1985-10-22 併合型不揮発性メモリセルマトリツクの書込み方法 Pending JPS6199997A (ja)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
IT8423281A IT1213228B (it)	1984-10-23	1984-10-23	Metodo di scrittura per matrice di celle di memoria non volatile di tipo merged.
IT23281A/84		1984-10-23

Publications (1)

Publication Number	Publication Date
JPS6199997A true JPS6199997A (ja)	1986-05-19

Family

ID=11205614

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
JP60234659A Pending JPS6199997A (ja)	1984-10-23	1985-10-22	併合型不揮発性メモリセルマトリツクの書込み方法

Country Status (6)

Country	Link
JP (1)	JPS6199997A (it)
DE (1)	DE3537046A1 (it)
FR (1)	FR2572212B1 (it)
GB (1)	GB2166019B (it)
IT (1)	IT1213228B (it)
NL (1)	NL8502731A (it)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS6325981A (ja) *	1986-05-30	1988-02-03	アトメル・コーポレイション	電気的にブロツク消去可能なｅｅｐｒｏｍ
JPS6421795A (en) *	1987-07-15	1989-01-25	Mitsubishi Electric Corp	Writing and erasing method for nonvolatile semiconductor storage device
JPS6439694A (en) *	1987-08-05	1989-02-09	Mitsubishi Electric Corp	Non-volatile semiconductor memory device
JPH01289170A (ja) *	1988-05-16	1989-11-21	Toshiba Corp	不揮発性半導体記憶装置
JPH0223595A (ja) *	1988-07-12	1990-01-25	Mitsubishi Electric Corp	不揮発性半導体記憶装置の書込み方法
US9030877B2 (en)	2007-08-30	2015-05-12	Infineon Technologies Ag	Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4377857A (en) *	1980-11-18	1983-03-22	Fairchild Camera & Instrument	Electrically erasable programmable read-only memory
EP0085260B1 (en) *	1981-12-29	1989-08-02	Fujitsu Limited	Nonvolatile semiconductor memory circuit

1984
- 1984-10-23 IT IT8423281A patent/IT1213228B/it active
1985
- 1985-09-30 GB GB08524039A patent/GB2166019B/en not_active Expired
- 1985-10-07 NL NL8502731A patent/NL8502731A/nl not_active Application Discontinuation
- 1985-10-17 DE DE19853537046 patent/DE3537046A1/de not_active Withdrawn
- 1985-10-22 JP JP60234659A patent/JPS6199997A/ja active Pending
- 1985-10-23 FR FR858515758A patent/FR2572212B1/fr not_active Expired

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS6325981A (ja) *	1986-05-30	1988-02-03	アトメル・コーポレイション	電気的にブロツク消去可能なｅｅｐｒｏｍ
JPS6421795A (en) *	1987-07-15	1989-01-25	Mitsubishi Electric Corp	Writing and erasing method for nonvolatile semiconductor storage device
JPS6439694A (en) *	1987-08-05	1989-02-09	Mitsubishi Electric Corp	Non-volatile semiconductor memory device
JPH01289170A (ja) *	1988-05-16	1989-11-21	Toshiba Corp	不揮発性半導体記憶装置
JPH0223595A (ja) *	1988-07-12	1990-01-25	Mitsubishi Electric Corp	不揮発性半導体記憶装置の書込み方法
US9030877B2 (en)	2007-08-30	2015-05-12	Infineon Technologies Ag	Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number	Publication date
IT1213228B (it)	1989-12-14
FR2572212B1 (fr)	1989-05-19
NL8502731A (nl)	1986-05-16
FR2572212A1 (fr)	1986-04-25
DE3537046A1 (de)	1986-04-24
GB2166019B (en)	1988-06-02
IT8423281A0 (it)	1984-10-23
GB8524039D0 (en)	1985-11-06
GB2166019A (en)	1986-04-23

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