JPS62145342U - - Google Patents
Info
- Publication number
- JPS62145342U JPS62145342U JP1986031298U JP3129886U JPS62145342U JP S62145342 U JPS62145342 U JP S62145342U JP 1986031298 U JP1986031298 U JP 1986031298U JP 3129886 U JP3129886 U JP 3129886U JP S62145342 U JPS62145342 U JP S62145342U
- Authority
- JP
- Japan
- Prior art keywords
- heat conduction
- bump
- post
- hermetically sealed
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Description
第１図は本考案の実施例を示す開封図、第２図
は従来の気密封止型半導体装置を示す断面図であ
る。 １…半導体チツプ、１ａ…熱伝導用バンプ、２
…電気接続用ポスト、２ａ…熱伝導用ポスト、３
…電気接続用ワイヤ、４…キヤツプ、５…パツケ
ージ内配線、６…外部リード、７…キヤビテイ、
９…銅箔、１０…パツケージ、１１…電気接続用
端子。
は従来の気密封止型半導体装置を示す断面図であ
る。 １…半導体チツプ、１ａ…熱伝導用バンプ、２
…電気接続用ポスト、２ａ…熱伝導用ポスト、３
…電気接続用ワイヤ、４…キヤツプ、５…パツケ
ージ内配線、６…外部リード、７…キヤビテイ、
９…銅箔、１０…パツケージ、１１…電気接続用
端子。
Claims (1)
- 半導体チツプ表面に設けられた熱伝導用バンプ
と、前記熱伝導用バンプに対応するパツケージ位
置に設けられた熱伝導用ポストと、前記熱伝導用
バンプと前記熱伝導用ポストを接続する熱伝導率
の高い金属板とを有する気密封止型半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986031298U JPS62145342U (ja) | 1986-03-06 | 1986-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986031298U JPS62145342U (ja) | 1986-03-06 | 1986-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62145342U true JPS62145342U (ja) | 1987-09-12 |
Family
ID=30836902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986031298U Pending JPS62145342U (ja) | 1986-03-06 | 1986-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62145342U (ja) |
-
1986
- 1986-03-06 JP JP1986031298U patent/JPS62145342U/ja active Pending