JPS6237973A - Metal-electrode forming method - Google Patents
Metal-electrode forming methodInfo
- Publication number
- JPS6237973A JPS6237973A JP17796085A JP17796085A JPS6237973A JP S6237973 A JPS6237973 A JP S6237973A JP 17796085 A JP17796085 A JP 17796085A JP 17796085 A JP17796085 A JP 17796085A JP S6237973 A JPS6237973 A JP S6237973A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- forming
- resist
- gate electrode
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 9
- 229920003229 poly(methyl methacrylate) Polymers 0.000 abstract description 8
- 239000004926 polymethyl methacrylate Substances 0.000 abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 abstract description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 abstract description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 1
- 238000010894 electron beam technology Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000035945 sensitivity Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- XSTXAVWGXDQKEL-UHFFFAOYSA-N Trichloroethylene Chemical group ClC=C(Cl)Cl XSTXAVWGXDQKEL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- WSGCRAOTEDLMFQ-UHFFFAOYSA-N nonan-5-one Chemical compound CCCCC(=O)CCCC WSGCRAOTEDLMFQ-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、金属電極形成方法、特にショットキー障壁形
ゲート構造電界効果トランジスタ（以下、ＭＥＳＦＥＴ
と略称する）におけるゲート電極の形成に有効な電極形
成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming metal electrodes, particularly to a Schottky barrier gate structure field effect transistor (hereinafter referred to as MESFET).
The present invention relates to an electrode forming method effective for forming a gate electrode in the invention.
従来の技術
従来、ＭＥＳＦＥＴのゲート電極形成方法は、第２図ａ
−ｅに示すよう々工程が一般的であっ丸詳しくのべる
と、まず、第２図ａに示すように、Ｇ ａ Ａ ｓ活性
層１上に低感度ポジ形レジスト２およびその上に高感度
ポジ形レジスト３をそれぞれ塗布し、ついで、これらを
、第２図すに示すように、電子ビーム４を用いてゲート
電極パターンに露光する。そして、第２図Ｃに示すよう
に、所定の現像過程によって丁字形のレジスト開口断面
６を得る。ここで、下層レジスト２に比べ、上層レジス
ト３のパターン幅が広くなるのは、土層レジスト３が高
感度であるため、溶解速度が下層レジスト２に比べ大き
くなるからである。次に、第２図ｄに示すように、ゲー
ト電極用の金属６を蒸着する。Conventional technology The conventional method for forming the gate electrode of MESFET is shown in Fig. 2a.
The process shown in FIG. A shaped resist 3 is applied respectively, and these are then exposed to a gate electrode pattern using an electron beam 4, as shown in FIG. Then, as shown in FIG. 2C, a T-shaped resist opening cross section 6 is obtained by a predetermined development process. Here, the reason why the pattern width of the upper resist 3 is wider than that of the lower resist 2 is because the earth resist 3 has a high sensitivity and therefore has a higher dissolution rate than the lower resist 2. Next, as shown in FIG. 2d, a metal 6 for a gate electrode is deposited.
最後に、第２図ｅに示すように、レジスト２，３を除去
するリフトオフにより、断面丁字形のゲート電極７を得
る。Finally, as shown in FIG. 2e, the resists 2 and 3 are removed by lift-off to obtain the gate electrode 7 having a T-shaped cross section.
発明が解決しようとする問題点
このような従来のゲ−１・電極形成方法では、断面丁字
形のグーｉ・電極の上面電極幅および下面電極幅の各パ
ターン幅の制御が難しいという問題点があった。その理
由は、レジスト断面形状が丁字形となる２種類のレジス
トの組み合ぜと、露光。Problems to be Solved by the Invention In such a conventional method for forming the gate electrode, there is a problem in that it is difficult to control the pattern widths of the top electrode width and the bottom electrode width of the goo electrode, which has a T-shaped cross section. there were. The reason for this is the combination of two types of resist that have a T-shaped resist cross section, and the exposure.
現像の制御が難しいからである。さらに、リフトオフが
難しいという問題点もあった。そのだめに、再現性よく
断面丁字形のゲート電極を形成することができ々かった
。丑だ、このような断面丁字形のゲート電極は、上面部
が下面部より大きい構造であるだめに物理的強度が不足
しており、ゲート電極が破損しやすいという問題点があ
った。本発明はこのような問題点を解決するもので、高
精度のパターン幅制御が可能で、再現性のよく、しかも
物理的強度が充分なゲート電極の製作を目的としている
。This is because it is difficult to control development. Furthermore, there was also the problem that lift-off was difficult. As a result, it was not possible to form a gate electrode with a T-shaped cross section with good reproducibility. Unfortunately, such a gate electrode having a T-shaped cross section has a structure in which the upper surface is larger than the lower surface, and therefore lacks physical strength, resulting in a problem in that the gate electrode is easily damaged. The present invention is intended to solve these problems, and aims to manufacture a gate electrode that allows highly accurate pattern width control, has good reproducibility, and has sufficient physical strength.
問題点を解決するだめの手段
この問題を解決するために、本発明は半導体基板−にの
絶縁性薄膜に所定形状の開口パターンを形成する工程、
前記薄膜の厚さよりも厚い金属薄膜を全面に形成する工
程、前記所定形状の開口パターン全域を含む前記金属薄
膜上の所定領域にレジストマスクをパターン形成する工
程、前記レジストマスクを用いて前記金属薄膜をエツチ
ングする工程をそなえた金属電極形成方法である。Means for Solving the Problem In order to solve this problem, the present invention includes a step of forming an opening pattern of a predetermined shape in an insulating thin film on a semiconductor substrate.
a step of forming a metal thin film thicker than the thickness of the thin film over the entire surface; a step of patterning a resist mask in a predetermined area on the metal thin film including the entire area of the opening pattern of the predetermined shape; This is a metal electrode forming method that includes a step of etching.
作 用
この構成により、高精度のパターン幅制御が可能であり
、再現性がよく、しかも充分な物理的強度を持つ断面丁
字形のゲート電極を形成することができる。Function: With this configuration, it is possible to control the pattern width with high precision, and it is possible to form a gate electrode having a T-shaped cross section with good reproducibility and sufficient physical strength.
５実施例
第１図ａ −ｉは本発明の一実施例によるＭＥＳＦＥＴ
における断面丁字形のゲ−］・電極形成方法を示す工程
順断面図である。第１図ａに示すように、Ｇ ａ Ａ
ｓ活性層８」二にプラズマ気相成長法（ＰＣＶＤ）によ
タテＳｉ３Ｎ４膜９を２０００〜４ｏ００人の厚さに成
長させ、その上にポリメチルメタクリレート（ＰＭＭＡ
）レジスト１０を厚さ５０００人、スピンコードによ
って塗布する。ＰＭＭＡレジスト１ｏを硬膜化するため
に１７０℃で２ｏ分間ベーキングした後、第１図すに示
すように、電子ビーム４によって、露光量６４μａ、／
ｃｕｔでゲートパターンを描画し、次に、第１図Ｃに示
すように、メチルインブチルケトン（ＭＩ ＢＫ ）に
よる４分間の現像によって、ＰＭＭＡレジス）１０にゲ
ート電極同形パターンを得る。ついで、ＰＭＭＡレジス
ト１０をマスクとして、第１図ｄに示すように、ＣＦ４
，０２混合ガスによるドライエツチングによって、Ｓｉ
３Ｎ４膜９をエツチングする。このエツチング時間には
平行平板ドライエツチング装置を用い、条件はパワー７
００Ｗ、ＣＦ４５）圧ｏ、１２ＴＯｒｒ、ＰＯ２／Ｐｏ
Ｆ４−１．５．Ｓｉ３Ｎ４エツチングレート６００人／
分で、エツチング時間は１３分である。次に、第１図ｅ
に示すようにＧ ａ Ａ ｓ活性層８を硫酸：過酸化水
素：水−８：１ ：１の混合液でエツチングする。この
過程でＧ ａ Ａ ｓ活性層８はＳｉ３Ｎ４膜９を開口
部にオーバノ・ング状におおって食刻凹部が形成される
。ついで、第１図ｆに示すように、ＰＭＭＡレジスト１
ｏをトリクロルエチレンのボイルによって除去し、第１
図ｑに示すように、ゲート電極用金属のアルミニウムＡ
／一層１１を厚さ１μｍ、真空蒸着法によってＧ ａ
Ａ ｓ基板の露出部を含む全面に蒸着する。次に蒸着さ
れたＡｔ １１−トに例えば、ネガ形電子ビームレジス
ト、たとえば、東洋ソーダ社製商品名ａＭ−ＣＭＦ３を
６０ｏＯへの厚さにスピンコードによって塗布した後、
１３５℃で２０分間ベーキングする。次にドーズ量５ｏ
μＣ／／７で、ゲート電極用間ロバターンを含み、これ
より広い面積の所定の領域を電子ビーム露光し、さらに
、たとえばシクロヘキサノンとエチルセロソルブの３ニ
アからなる現像液で前記ネガ形電子ピームレジス）ａＭ
−ＣＭＳの現像をおこない、第１図りのように、レジス
トパターン１２を得る。そして、最終的には、第１図ｉ
に示すように、レジス）（ＺＭ−０ＭＳパターン１２を
マスクとして、ＣＣｔ４ガスによるＲＩＥによってＡｔ
１１をエツチングし、アセトンのボイルによって、Ａｔ
１１上のレジスト１２を除去することでＳｉ３Ｎ４膜８
に支持された断面丁字形のゲート電極を得る。なお、Ａ
ｔ １１のエツチング条件は、エツチング圧力８Ｐａ、
エツチング電力密度ｏ、２５Ｗ／ｃｒＡ 、 ＣＣ
ｔ４ガス流量１００ ｃｃ ７分 であり、Ａｔエツチ
ングレートに１．２０００人／分、エツチング時間（１
７１−６分３０秒である。5 Embodiment FIGS. 1a-i are MESFETs according to an embodiment of the present invention.
FIG. 3 is a step-by-step cross-sectional view showing a method for forming a gate electrode having a T-shaped cross section. As shown in Figure 1a, G a A
A vertical Si3N4 film 9 is grown on the active layer 8 by plasma vapor deposition (PCVD) to a thickness of 2,000 to 4,000 mm, and polymethyl methacrylate (PMMA) is deposited on top of it.
) Apply resist 10 to a thickness of 5,000 yen using a spin cord. After baking the PMMA resist 1o at 170° C. for 20 minutes to harden it, it was exposed to an electron beam 4 with an exposure dose of 64 μa, as shown in FIG.
A gate pattern is drawn by cut, and then, as shown in FIG. 1C, a gate electrode conformal pattern is obtained on the PMMA resist 10 by development with methyl in butyl ketone (MI BK ) for 4 minutes. Next, using the PMMA resist 10 as a mask, as shown in FIG.
,02 mixed gas by dry etching, Si
Etch the 3N4 film 9. A parallel plate dry etching device was used for this etching time, and the conditions were power 7.
00W, CF45) Pressure o, 12Torr, PO2/Po
F4-1.5. Si3N4 etching rate 600 people/
minutes, and the etching time is 13 minutes. Next, Figure 1 e
As shown in Figure 2, the GaAs active layer 8 is etched with a mixture of sulfuric acid: hydrogen peroxide: water - 8:1:1. In this process, the GaAs active layer 8 covers the opening with the Si3N4 film 9 in an overhang shape to form an etched recess. Then, as shown in FIG. 1f, PMMA resist 1
o was removed by boiling in trichlorethylene and the first
As shown in Figure q, the gate electrode metal aluminum A
/G a layer 11 with a thickness of 1 μm by vacuum evaporation method
Deposit on the entire surface of the A s substrate, including the exposed parts. Next, a negative electron beam resist, such as aM-CMF3 manufactured by Toyo Soda Co., Ltd., is applied to the deposited At 11-t by a spin cord to a thickness of 60oO.
Bake at 135°C for 20 minutes. Next, the dose is 5o
μC//7 is used to expose a predetermined area including the gate electrode gap pattern and a wider area to an electron beam, and then the negative electron beam resist (aM
-Develop the CMS to obtain a resist pattern 12 as shown in the first drawing. And finally, Figure 1 i
As shown in FIG.
11 and boiled in acetone to form At
By removing the resist 12 on 11, the Si3N4 film 8
A gate electrode with a T-shaped cross section supported by the gate electrode is obtained. In addition, A
The etching conditions at t11 were an etching pressure of 8 Pa,
Etching power density o, 25W/crA, CC
The t4 gas flow rate was 100 cc for 7 minutes, the At etching rate was 1.2000 people/min, and the etching time (1
71-6 minutes and 30 seconds.
発明の効果
以上のように、本発明によれば、断面丁字形のゲート電
極の下面のパターン幅は、はじめに形成した絶縁膜の開
口パターン幅により決定される。Effects of the Invention As described above, according to the present invention, the pattern width of the lower surface of the gate electrode having a T-shaped cross section is determined by the opening pattern width of the insulating film formed first.
捷だ、同断面丁字形のゲート電極の」二面のパターン幅
は、２回目のリングラフィ工程により決定される。従っ
て同電極の上面および下面のパターン幅を独立に、高精
度、再現性よく制御することができる。さらに、断面丁
字形のゲート電極は、絶縁性薄膜により支持されている
ので、充分な物理的強度を持っている。しかも、ゲート
電極の上面部と接触する絶縁性薄膜は、Ｇ ａ Ａ ｓ
活性層の食刻四部形成、いわゆる、リセスエッチングの
マスク材として利用することもでき、かかるリセス構造
にすることにより、直接Ｇ ａ Ａ ｓ活性層と接触し
ない。このことによって、容量の増加を最小限におさえ
、しかも耐圧向上を達成することができる。The pattern width on two sides of the gate electrode, which has the same T-shaped cross section, is determined by the second phosphorography process. Therefore, the pattern widths of the upper and lower surfaces of the electrode can be controlled independently with high precision and good reproducibility. Furthermore, since the gate electrode having a T-shaped cross section is supported by an insulating thin film, it has sufficient physical strength. Moreover, the insulating thin film in contact with the upper surface of the gate electrode is
It can also be used as a mask material for forming four parts of the active layer, so-called recess etching, and by forming such a recessed structure, it does not come into direct contact with the GaAs active layer. This makes it possible to minimize the increase in capacity and improve the breakdown voltage.
以上のように、本発明によれば、高精度のパターン幅制
御が可能であり、再現性がよく、しかも充分な物理的強
度を持つ断面丁字形のゲート電極を形成することができ
る。As described above, according to the present invention, it is possible to control the pattern width with high accuracy, and form a gate electrode having a T-shaped cross section with good reproducibility and sufficient physical strength.
第１図 は、本発明の一実施例によるＭＥＳＦＥＴ
における断面丁字形のゲート電極形成方法を示す工
程順断面図、第２図は、従来の電極形成方法を示す工程
順断面図である。
１．８・・・・・Ｇ ａ Ａ ｓ活性層、２・・・・・
・低感度ポジ形レジスト、３・・・・・高感度ポジ形レ
ジスト、４・・・電子ビーム、５・・・・・・丁字形レ
ジスト開口断面、６・・・・・ゲート金属、７・・・−
丁字形ゲート電極、９・・・・・・Ｓｉ３Ｎ４膜、１０
・・・・−ＰＭＭＡレジスト、１１Ａｔ、１２・・・・
ネガ形電子ビームレジスト。FIG. 1 shows a MESFET according to an embodiment of the present invention.
FIG. 2 is a step-by-step sectional view showing a method for forming a gate electrode having a T-shaped cross section. FIG. 2 is a step-by-step sectional view showing a conventional electrode forming method. 1.8...G a As active layer, 2...
・Low sensitivity positive resist, 3... High sensitivity positive resist, 4... Electron beam, 5... T-shaped resist opening cross section, 6... Gate metal, 7.・・−
T-shaped gate electrode, 9...Si3N4 film, 10
...-PMMA resist, 11At, 12...
Negative electron beam resist.
Claims (2)
ーンを形成する工程、前記薄膜の厚さよりも厚い金属薄
膜を全面に形成する工程、前記所定形状の開口パターン
全域を含む前記金属薄膜上の所定領域にレジストマスク
をパターン形成する工程、前記レジストマスクを用いて
前記金属薄膜をエッチングする工程をそなえた金属電極
形成方法。(1) A step of forming an opening pattern of a predetermined shape in an insulating thin film on a semiconductor substrate, a step of forming a metal thin film that is thicker than the thickness of the thin film on the entire surface, and a step of forming an opening pattern of a predetermined shape on the entire surface of the metal thin film including the entire area of the opening pattern of the predetermined shape. A method for forming a metal electrode, comprising the steps of patterning a resist mask in a predetermined region of the metal electrode, and etching the metal thin film using the resist mask.
パターンでオーバハング状に覆われた食刻凹部をそなえ
たものでなる特許請求の範囲第１項記載の金属電極形成
方法。(2) The method of forming a metal electrode according to claim 1, wherein the semiconductor substrate is provided with an etched recess covered with an overhanging opening pattern of a predetermined shape in an insulating thin film directly above the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17796085A JPS6237973A (en) | 1985-08-13 | 1985-08-13 | Metal-electrode forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17796085A JPS6237973A (en) | 1985-08-13 | 1985-08-13 | Metal-electrode forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6237973A true JPS6237973A (en) | 1987-02-18 |
Family
ID=16040088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17796085A Pending JPS6237973A (en) | 1985-08-13 | 1985-08-13 | Metal-electrode forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6237973A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63204772A (en) * | 1987-02-20 | 1988-08-24 | Sharp Corp | Manufacture of semiconductor device |
| US5139968A (en) * | 1989-03-03 | 1992-08-18 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a t-shaped gate electrode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57204175A (en) * | 1981-06-11 | 1982-12-14 | Nec Corp | Manufacture of semiconductor device |
| JPS58115868A (en) * | 1981-12-28 | 1983-07-09 | Fujitsu Ltd | Manufacture of field-effect transistor |
-
1985
- 1985-08-13 JP JP17796085A patent/JPS6237973A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57204175A (en) * | 1981-06-11 | 1982-12-14 | Nec Corp | Manufacture of semiconductor device |
| JPS58115868A (en) * | 1981-12-28 | 1983-07-09 | Fujitsu Ltd | Manufacture of field-effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63204772A (en) * | 1987-02-20 | 1988-08-24 | Sharp Corp | Manufacture of semiconductor device |
| US5139968A (en) * | 1989-03-03 | 1992-08-18 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a t-shaped gate electrode |
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