JPS6251442U - - Google Patents
Info
- Publication number
- JPS6251442U JPS6251442U JP12799486U JP12799486U JPS6251442U JP S6251442 U JPS6251442 U JP S6251442U JP 12799486 U JP12799486 U JP 12799486U JP 12799486 U JP12799486 U JP 12799486U JP S6251442 U JPS6251442 U JP S6251442U
- Authority
- JP
- Japan
- Prior art keywords
- parity
- data
- processing unit
- central processing
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005856 abnormality Effects 0.000 claims 3
- 238000012795 verification Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は従来の方式の一例のブロツク図、第２
図は本考案のパリテイチエツク回路の一実施例の
ブロツク図である。
ＣＰＵ……マイクロコンピユータ、ＭＥＭ……
メモリ、ＰＣ……パリテイチエツク回路、ＰＧ…
…パリテイビツト発生回路、ＯＲ……論理和ゲー
ト回路、ＡＮＤ……論理積ゲート回路、ＡＢｏ，
ＡＢ１，…，ＡＢｊ……アドレスバス、ＤＢｏ，
ＤＢ１，…，ＤＢｎ……データバス、Ａｏ，Ａ１
，…，Ａｊ……アドレスバス情報端子、Ｄｏ，Ｄ
１，…，Ｄｎ……データバス情報端子、Ｗ……書
込み情報信号端子、Ｒ……読出し情報信号端子、
ＲＤＹ……周辺装置準備可能情報信号端子、ＲＳ
Ｔ……初期設定情報信号端子、ＩＮＴ……割込み
情報信号端子、Ｐ……パリテイビツト情報信号端
子、ＯＫ……パリテイ正常信号端子、ＥＲＲ……
パリテイ異常信号端子。
Figure 1 is a block diagram of an example of a conventional method; Figure 2 is a block diagram of an example of a conventional method;
The figure is a block diagram of one embodiment of the parity check circuit of the present invention. CPU...Microcomputer, MEM...
Memory, PC... parity check circuit, PG...
...Parity bit generation circuit, OR...OR gate circuit, AND...AND gate circuit, ABo,
AB1,...,ABj...address bus, DBo,
DB1,...,DBn...data bus, Ao, A1
,...,Aj...Address bus information terminal, Do, D
1,...,Dn...Data bus information terminal, W...Write information signal terminal, R...Read information signal terminal,
RDY...Peripheral device ready information signal terminal, RS
T...Initial setting information signal terminal, INT...Interrupt information signal terminal, P...Parity bit information signal terminal, OK...Parity normal signal terminal, ERR...
Parity error signal terminal.
Claims (1)
構成される中央処理装置が、記憶装置との間でデ
ータの書込みおよび読出しを行なうデータ処理装
置において、 前記データバスに接続され、かつ前記中央処理
装置が前記記憶装置に前記データを書込むとき、
前記中央処理装置の制御に従つて書込まれる前記
データのパリテイに従い、所定のパリテイビツト
を発生し、かつ前記中央処理装置が前記記憶装置
に前記データとともに前記パリテイビツトを書込
めるように前記パリテイビツトを出力するパリテ
イビツト発生回路と、 前記データバスに接続され、かつ前記中央処理
装置が前記記憶装置から前記データを読出すとき
、前記中央処理装置の制御に従つて前記記憶装置
から前記データとともに読出される前記パリテイ
ビツトに従い読出される前記データのパリテイを
検定し、かつその検定の結果続出される前記デー
タのパリテイが正常であるときは前記中央処理装
置を構成するマイクロコンピユータの周辺装置準
備可能情報信号端子に前記中央処理装置が正常処
理動作を続行するようにパリテイ正常信号を出力
し、異常であるときには前記中央処理装置を構成
するマイクロコンピユータの初期設定情報信号端
子および割込み情報信号端子のいずれかに前記中
央処理装置が異常処理動作を開始するようにパリ
テイ異常信号を出力するパリテイチエツク回路と
、 を備えることを特徴とするパリテイチエツク回路
。[Claims for Utility Model Registration] A data processing device in which a central processing unit composed of a microcomputer writes and reads data to and from a storage device via a data bus, and When the central processing unit writes the data to the storage device,
Generating a predetermined parity bit according to the parity of the data written under the control of the central processing unit, and outputting the parity bit so that the central processing unit can write the parity bit together with the data in the storage device. a parity bit generation circuit, the parity bit being connected to the data bus and read together with the data from the storage device under control of the central processing unit when the central processing unit reads the data from the storage device. The parity of the data read out according to the above is verified, and if the parity of the data successively read out is normal as a result of the verification, the central A parity normal signal is output so that the processing unit continues normal processing operation, and when an abnormality occurs, the parity normal signal is output to either the initial setting information signal terminal or the interrupt information signal terminal of the microcomputer that constitutes the central processing unit. A parity check circuit comprising: a parity check circuit that outputs a parity abnormality signal so that a parity error signal starts an abnormality processing operation;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12799486U JPS6230105Y2 (en) | 1986-08-22 | 1986-08-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12799486U JPS6230105Y2 (en) | 1986-08-22 | 1986-08-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6251442U true JPS6251442U (en) | 1987-03-31 |
| JPS6230105Y2 JPS6230105Y2 (en) | 1987-08-03 |
Family
ID=31023260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12799486U Expired JPS6230105Y2 (en) | 1986-08-22 | 1986-08-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6230105Y2 (en) |
-
1986
- 1986-08-22 JP JP12799486U patent/JPS6230105Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6230105Y2 (en) | 1987-08-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6251442U (en) | ||
| JPS6146864B2 (en) | ||
| JPS623520B2 (en) | ||
| JPH0435957Y2 (en) | ||
| JP2751878B2 (en) | Multiprocessor device | |
| JPS586172B2 (en) | Interface method | |
| JPS6020099U (en) | P-ROM writer | |
| JPS6116652U (en) | Memory data display tester | |
| JPS6261977B2 (en) | ||
| JPS59119661U (en) | image memory device | |
| JPS61235963A (en) | Packet password access system | |
| JPH0474341U (en) | ||
| JPH10289160A (en) | Write data security method for semiconductor memory | |
| JPH0697395B2 (en) | Electronic musical instrument | |
| JPS647356U (en) | ||
| JPH01133645U (en) | ||
| JPS58101252U (en) | Parity checker malfunction prevention circuit | |
| JPH0358217A (en) | Electronic disk subsystem | |
| JPH023183A (en) | Eeprom writing completion confirming system | |
| JPS6368052U (en) | ||
| JPH02116346U (en) | ||
| JPH0514293B2 (en) | ||
| JPH01174929U (en) | ||
| JPH0474340U (en) | ||
| JPS61204262U (en) |