JPS6352461B2 - - Google Patents
Info
- Publication number
- JPS6352461B2 JPS6352461B2 JP54146249A JP14624979A JPS6352461B2 JP S6352461 B2 JPS6352461 B2 JP S6352461B2 JP 54146249 A JP54146249 A JP 54146249A JP 14624979 A JP14624979 A JP 14624979A JP S6352461 B2 JPS6352461 B2 JP S6352461B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gold
- germanium
- ceramic body
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07336—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14624979A JPS5669839A (en) | 1979-11-12 | 1979-11-12 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14624979A JPS5669839A (en) | 1979-11-12 | 1979-11-12 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5669839A JPS5669839A (en) | 1981-06-11 |
| JPS6352461B2 true JPS6352461B2 (fr) | 1988-10-19 |
Family
ID=15403457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14624979A Granted JPS5669839A (en) | 1979-11-12 | 1979-11-12 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5669839A (fr) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2567442B2 (ja) * | 1988-02-22 | 1996-12-25 | 住友電気工業株式会社 | 半導体装置及びその製造方法 |
| JP3372511B2 (ja) * | 1999-08-09 | 2003-02-04 | ソニーケミカル株式会社 | 半導体素子の実装方法及び実装装置 |
-
1979
- 1979-11-12 JP JP14624979A patent/JPS5669839A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5669839A (en) | 1981-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW419761B (en) | Chip size package and method of fabricating the same | |
| JP3420703B2 (ja) | 半導体装置の製造方法 | |
| US20070085201A1 (en) | Power semiconductor device in lead frame technology with a vertical current path | |
| US3706915A (en) | Semiconductor device with low impedance bond | |
| EP0090566B1 (fr) | Empaquetage pour dispositif semi-conducteur | |
| GB2138633A (en) | Bonding semiconductor chips to a lead frame | |
| JPH06501816A (ja) | 合成ハイブリッド半導体ストラクチャ | |
| US20020095784A1 (en) | Bumping process for chip scale packaging | |
| US3480842A (en) | Semiconductor structure disc having pn junction with improved heat and electrical conductivity at outer layer | |
| JPS6352461B2 (fr) | ||
| JPS5850021B2 (ja) | 半導体装置の製法 | |
| JP2503738B2 (ja) | リ―ドフレ―ムへの半導体素子の接合方法 | |
| JPH1084011A (ja) | 半導体装置及びこの製造方法並びにその実装方法 | |
| JPS61181136A (ja) | ダイボンデイング方法 | |
| JP3446829B2 (ja) | 半導体装置 | |
| JPH0525182B2 (fr) | ||
| JP3645391B2 (ja) | 半導体集積回路装置の製造方法 | |
| JPH02168640A (ja) | 異なる基板間の接続構造 | |
| JP2986661B2 (ja) | 半導体装置の製造方法 | |
| JPH1032275A (ja) | 半導体装置およびその製造方法 | |
| JPH08115947A (ja) | 半導体装置の接合構造 | |
| JPH03208355A (ja) | 半導体装置及びその製造方法 | |
| JPS6025900Y2 (ja) | 半導体装置 | |
| WO2025027916A1 (fr) | Dispositif à semi-conducteurs, dispositif d'alimentation électrique, et module d'alimentation électrique | |
| JPS61171153A (ja) | 半導体装置 |