JPS636735U - - Google Patents

Info

Publication number
JPS636735U
JPS636735U JP1986101093U JP10109386U JPS636735U JP S636735 U JPS636735 U JP S636735U JP 1986101093 U JP1986101093 U JP 1986101093U JP 10109386 U JP10109386 U JP 10109386U JP S636735 U JPS636735 U JP S636735U
Authority
JP
Japan
Prior art keywords
relay terminal
wiring pattern
auxiliary relay
terminal board
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1986101093U
Other languages
English (en)
Other versions
JPH0436110Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986101093U priority Critical patent/JPH0436110Y2/ja
Publication of JPS636735U publication Critical patent/JPS636735U/ja
Application granted granted Critical
Publication of JPH0436110Y2 publication Critical patent/JPH0436110Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案による一実施例を示す半導体装
置の斜視図、第２図は本考案による一実施例を示
す半導体装置の平面図、第３図は本考案の補助中
継端子板の構造を示す図、第４図は変更仕様に対
する従来技術を示す半導体装置の平面図、第５図
は設計仕様による半導体装置の平面図、である。 図において、１はケース、２は半導体素子、３
はリード、３ａは内部リード、３ｂは外部リード
、４は補助中継端子、４ａは絶縁基板、４ｂは配
線パターン、４ｃはボンデイングランド、５は素
子取付台、である。

Claims (1)

    【実用新案登録請求の範囲】
  1. リード３を絶縁物を介して側壁に設けた収納容
    器１の該側壁の内側に補助中継端子板４を設け、
    該補助中継端子板４は絶縁基板４ａ上に配線パタ
    ーン４ｂをメタライズ加工により形成し、ボンデ
    イングランド４ｃを該配線パターン４ｂ上に銀ろ
    う付けしたことを特徴とする半導体装置。
JP1986101093U 1986-06-30 1986-06-30 Expired JPH0436110Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986101093U JPH0436110Y2 (ja) 1986-06-30 1986-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986101093U JPH0436110Y2 (ja) 1986-06-30 1986-06-30

Publications (2)

Publication Number Publication Date
JPS636735U true JPS636735U (ja) 1988-01-18
JPH0436110Y2 JPH0436110Y2 (ja) 1992-08-26

Family

ID=30971522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986101093U Expired JPH0436110Y2 (ja) 1986-06-30 1986-06-30

Country Status (1)

Country Link
JP (1) JPH0436110Y2 (ja)

Also Published As

Publication number Publication date
JPH0436110Y2 (ja) 1992-08-26

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