JPS647548A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS647548A
JPS647548A JP63001390A JP139088A JPS647548A JP S647548 A JPS647548 A JP S647548A JP 63001390 A JP63001390 A JP 63001390A JP 139088 A JP139088 A JP 139088A JP S647548 A JPS647548 A JP S647548A
Authority
JP
Japan
Prior art keywords
polishing
layer
grooves
depths
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63001390A
Other languages
English (en)
Other versions
JP2847671B2 (ja
Inventor
Maria Reonteina Arek Erizabesu
Haisuma Yan
Maruchinusu Mihierus Seodorasu
Uiruherumusu Adorianu Yohanesu
Furanshisukasu Korine Yohanesu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of JPS647548A publication Critical patent/JPS647548A/ja
Application granted granted Critical
Publication of JP2847671B2 publication Critical patent/JP2847671B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/019—Manufacture or treatment of isolation regions comprising dielectric materials using epitaxial passivated integrated circuit [EPIC] processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/164—Three dimensional processing

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP63001390A 1987-01-09 1988-01-08 半導体装置の製造方法 Expired - Fee Related JP2847671B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8700033 1987-01-09
NL8700033A NL8700033A (nl) 1987-01-09 1987-01-09 Werkwijze voor het vervaardigen van een halfgeleiderinrichting van het type halfgeleider op isolator.

Publications (2)

Publication Number Publication Date
JPS647548A true JPS647548A (en) 1989-01-11
JP2847671B2 JP2847671B2 (ja) 1999-01-20

Family

ID=19849387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63001390A Expired - Fee Related JP2847671B2 (ja) 1987-01-09 1988-01-08 半導体装置の製造方法

Country Status (6)

Country Link
US (1) US4971925A (ja)
EP (1) EP0274801B1 (ja)
JP (1) JP2847671B2 (ja)
KR (1) KR970000648B1 (ja)
DE (1) DE3780795T2 (ja)
NL (1) NL8700033A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399233A (en) * 1991-12-05 1995-03-21 Fujitsu Limited Method of and apparatus for manufacturing a semiconductor substrate
JP2012199556A (ja) * 2000-03-22 2012-10-18 Ziptronix Inc 三次元デバイスの一体化方法および一体化されたデバイス
US10366962B2 (en) 1999-10-01 2019-07-30 Invensas Bonding Technologies, Inc. Three dimensional device integration method and integrated device
US11760059B2 (en) 2003-05-19 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Method of room temperature covalent bonding
US12424584B2 (en) 2020-10-29 2025-09-23 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8800953A (nl) * 1988-04-13 1989-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderlichaam.
JPH02146732A (ja) * 1988-07-28 1990-06-05 Fujitsu Ltd 研摩液及び研摩方法
EP0363100A3 (en) * 1988-10-02 1990-05-23 Canon Kabushiki Kaisha Selective polishing method
JP2577090B2 (ja) * 1989-08-07 1997-01-29 キヤノン株式会社 結晶半導体膜の形成方法
JP2541884B2 (ja) * 1991-08-31 1996-10-09 信越半導体株式会社 誘電体分離基板の製造方法
US5334281A (en) * 1992-04-30 1994-08-02 International Business Machines Corporation Method of forming thin silicon mesas having uniform thickness
US5234846A (en) * 1992-04-30 1993-08-10 International Business Machines Corporation Method of making bipolar transistor with reduced topography
US5258318A (en) * 1992-05-15 1993-11-02 International Business Machines Corporation Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
US5302842A (en) * 1992-07-20 1994-04-12 Bell Communications Research, Inc. Field-effect transistor formed over gate electrode
US5262346A (en) * 1992-12-16 1993-11-16 International Business Machines Corporation Nitride polish stop for forming SOI wafers
US5318663A (en) * 1992-12-23 1994-06-07 International Business Machines Corporation Method for thinning SOI films having improved thickness uniformity
WO2004077537A1 (ja) * 1993-01-18 2004-09-10 Shinsuke Sakai 半導体基板の製造方法
US5376580A (en) * 1993-03-19 1994-12-27 Hewlett-Packard Company Wafer bonding of light emitting diode layers
JP3301170B2 (ja) * 1993-08-09 2002-07-15 ソニー株式会社 半導体装置の製法
JP3033655B2 (ja) * 1993-09-28 2000-04-17 日本電気株式会社 半導体装置及び半導体装置の製造方法
US5358887A (en) * 1993-11-26 1994-10-25 United Microelectronics Corporation Ulsi mask ROM structure and method of manufacture
US5449638A (en) * 1994-06-06 1995-09-12 United Microelectronics Corporation Process on thickness control for silicon-on-insulator technology
US5496764A (en) * 1994-07-05 1996-03-05 Motorola, Inc. Process for forming a semiconductor region adjacent to an insulating layer
US6484585B1 (en) 1995-02-28 2002-11-26 Rosemount Inc. Pressure sensor for a pressure transmitter
US5637802A (en) * 1995-02-28 1997-06-10 Rosemount Inc. Capacitive pressure sensor for a pressure transmitted where electric field emanates substantially from back sides of plates
US5583072A (en) * 1995-06-30 1996-12-10 Siemens Components, Inc. Method of manufacturing a monolithic linear optocoupler
US5708264A (en) * 1995-11-07 1998-01-13 Eastman Kodak Company Planar color filter array for CCDs from dyed and mordant layers
US5677202A (en) * 1995-11-20 1997-10-14 Eastman Kodak Company Method for making planar color filter array for image sensors with embedded color filter arrays
US6508129B1 (en) 2000-01-06 2003-01-21 Rosemount Inc. Pressure sensor capsule with improved isolation
US6505516B1 (en) 2000-01-06 2003-01-14 Rosemount Inc. Capacitive pressure sensing with moving dielectric
US6520020B1 (en) 2000-01-06 2003-02-18 Rosemount Inc. Method and apparatus for a direct bonded isolated pressure sensor
US6561038B2 (en) 2000-01-06 2003-05-13 Rosemount Inc. Sensor with fluid isolation barrier
AU2629901A (en) 2000-01-06 2001-07-16 Rosemount Inc. Grain growth of electrical interconnection for microelectromechanical systems (mems)
US6848316B2 (en) 2002-05-08 2005-02-01 Rosemount Inc. Pressure sensor assembly

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5099685A (ja) * 1973-12-29 1975-08-07
JPS5099684A (ja) * 1973-12-29 1975-08-07
JPS57128942A (en) * 1981-02-02 1982-08-10 Jido Keisoku Gijutsu Kenkiyuukumiai Manufacture of insulation isolating substrate
JPS59188138A (ja) * 1983-04-08 1984-10-25 Nec Corp 半導体装置の製造方法
JPS6039835A (ja) * 1983-08-12 1985-03-01 Hitachi Ltd 基板表面の平坦化方法
JPS6356936A (ja) * 1986-08-27 1988-03-11 Nec Corp 半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508980A (en) * 1967-07-26 1970-04-28 Motorola Inc Method of fabricating an integrated circuit structure with dielectric isolation
US3689357A (en) * 1970-12-10 1972-09-05 Gen Motors Corp Glass-polysilicon dielectric isolation
US3938176A (en) * 1973-09-24 1976-02-10 Texas Instruments Incorporated Process for fabricating dielectrically isolated semiconductor components of an integrated circuit
US3911562A (en) * 1974-01-14 1975-10-14 Signetics Corp Method of chemical polishing of planar silicon structures having filled grooves therein
US4501060A (en) * 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
NL8501773A (nl) * 1985-06-20 1987-01-16 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen.
JPH0783050B2 (ja) * 1985-06-21 1995-09-06 株式会社東芝 半導体素子の製造方法
US4671851A (en) * 1985-10-28 1987-06-09 International Business Machines Corporation Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique
US4735679A (en) * 1987-03-30 1988-04-05 International Business Machines Corporation Method of improving silicon-on-insulator uniformity
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding
US4794092A (en) * 1987-11-18 1988-12-27 Grumman Aerospace Corporation Single wafer moated process
US4784970A (en) * 1987-11-18 1988-11-15 Grumman Aerospace Corporation Process for making a double wafer moated signal processor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5099685A (ja) * 1973-12-29 1975-08-07
JPS5099684A (ja) * 1973-12-29 1975-08-07
JPS57128942A (en) * 1981-02-02 1982-08-10 Jido Keisoku Gijutsu Kenkiyuukumiai Manufacture of insulation isolating substrate
JPS59188138A (ja) * 1983-04-08 1984-10-25 Nec Corp 半導体装置の製造方法
JPS6039835A (ja) * 1983-08-12 1985-03-01 Hitachi Ltd 基板表面の平坦化方法
JPS6356936A (ja) * 1986-08-27 1988-03-11 Nec Corp 半導体装置の製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399233A (en) * 1991-12-05 1995-03-21 Fujitsu Limited Method of and apparatus for manufacturing a semiconductor substrate
US10366962B2 (en) 1999-10-01 2019-07-30 Invensas Bonding Technologies, Inc. Three dimensional device integration method and integrated device
JP2012199556A (ja) * 2000-03-22 2012-10-18 Ziptronix Inc 三次元デバイスの一体化方法および一体化されたデバイス
JP2015084421A (ja) * 2000-03-22 2015-04-30 ジプトロニクス・インコーポレイテッド 三次元デバイスの一体化方法および一体化されたデバイス
JP2016178310A (ja) * 2000-03-22 2016-10-06 ジプトロニクス・インコーポレイテッド 三次元デバイスの一体化方法および一体化されたデバイス
US11760059B2 (en) 2003-05-19 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Method of room temperature covalent bonding
US12424584B2 (en) 2020-10-29 2025-09-23 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures

Also Published As

Publication number Publication date
US4971925A (en) 1990-11-20
NL8700033A (nl) 1988-08-01
DE3780795D1 (de) 1992-09-03
KR970000648B1 (ko) 1997-01-16
EP0274801A2 (en) 1988-07-20
JP2847671B2 (ja) 1999-01-20
EP0274801B1 (en) 1992-07-29
KR880009430A (ko) 1988-09-15
EP0274801A3 (en) 1988-08-17
DE3780795T2 (de) 1993-03-04

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees