KR920020594A - Ldd 트랜지스터의 구조 및 제조방법 - Google Patents
Ldd 트랜지스터의 구조 및 제조방법 Download PDFInfo
- Publication number
- KR920020594A KR920020594A KR1019910005714A KR910005714A KR920020594A KR 920020594 A KR920020594 A KR 920020594A KR 1019910005714 A KR1019910005714 A KR 1019910005714A KR 910005714 A KR910005714 A KR 910005714A KR 920020594 A KR920020594 A KR 920020594A
- Authority
- KR
- South Korea
- Prior art keywords
- low concentration
- drain region
- concentration source
- polysilicon
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/605—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having significant overlap between the lightly-doped extensions and the gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
- H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
- H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910005714A KR920020594A (ko) | 1991-04-10 | 1991-04-10 | Ldd 트랜지스터의 구조 및 제조방법 |
| TW081102330A TW268136B (2) | 1991-04-10 | 1992-03-26 | |
| DE4211999A DE4211999C2 (de) | 1991-04-10 | 1992-04-09 | LDD-Transistor und Verfahren zu dessen Herstellung |
| JP4116768A JP2547690B2 (ja) | 1991-04-10 | 1992-04-10 | Lddトランジスタの製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910005714A KR920020594A (ko) | 1991-04-10 | 1991-04-10 | Ldd 트랜지스터의 구조 및 제조방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR920020594A true KR920020594A (ko) | 1992-11-21 |
Family
ID=19313084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910005714A Ceased KR920020594A (ko) | 1991-04-10 | 1991-04-10 | Ldd 트랜지스터의 구조 및 제조방법 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2547690B2 (2) |
| KR (1) | KR920020594A (2) |
| DE (1) | DE4211999C2 (2) |
| TW (1) | TW268136B (2) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5518945A (en) * | 1995-05-05 | 1996-05-21 | International Business Machines Corporation | Method of making a diffused lightly doped drain device with built in etch stop |
| US6339005B1 (en) * | 1999-10-22 | 2002-01-15 | International Business Machines Corporation | Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET |
| US7732285B2 (en) * | 2007-03-28 | 2010-06-08 | Intel Corporation | Semiconductor device having self-aligned epitaxial source and drain extensions |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6143477A (ja) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Mosトランジスタの製造方法 |
| JPH06105715B2 (ja) * | 1985-03-20 | 1994-12-21 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
| JPH01309376A (ja) * | 1988-06-07 | 1989-12-13 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
-
1991
- 1991-04-10 KR KR1019910005714A patent/KR920020594A/ko not_active Ceased
-
1992
- 1992-03-26 TW TW081102330A patent/TW268136B/zh active
- 1992-04-09 DE DE4211999A patent/DE4211999C2/de not_active Expired - Fee Related
- 1992-04-10 JP JP4116768A patent/JP2547690B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0629308A (ja) | 1994-02-04 |
| DE4211999A1 (de) | 1992-10-15 |
| JP2547690B2 (ja) | 1996-10-23 |
| TW268136B (2) | 1996-01-11 |
| DE4211999C2 (de) | 1999-06-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
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| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
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| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
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| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
St.27 status event code: N-2-6-B10-B15-exm-PE0601 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-3-3-R10-R13-asn-PN2301 St.27 status event code: A-3-3-R10-R11-asn-PN2301 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
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| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
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| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |