SG81964A1 - Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof - Google Patents

Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof

Info

Publication number
SG81964A1
SG81964A1 SG9900611A SG1999000611A SG81964A1 SG 81964 A1 SG81964 A1 SG 81964A1 SG 9900611 A SG9900611 A SG 9900611A SG 1999000611 A SG1999000611 A SG 1999000611A SG 81964 A1 SG81964 A1 SG 81964A1
Authority
SG
Singapore
Prior art keywords
semiconductor substrate
composite member
preparation
base
utilization
Prior art date
Application number
SG9900611A
Other languages
English (en)
Inventor
Ohmi Kazuaki
Sakaguchi Kiyofumi
Yanagita Kazutaka
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Publication of SG81964A1 publication Critical patent/SG81964A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
SG9900611A 1998-02-18 1999-02-15 Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof SG81964A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3582098 1998-02-18

Publications (1)

Publication Number Publication Date
SG81964A1 true SG81964A1 (en) 2001-07-24

Family

ID=12452596

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9900611A SG81964A1 (en) 1998-02-18 1999-02-15 Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof

Country Status (9)

Country Link
US (2) US6342433B1 (fr)
EP (1) EP0938129B1 (fr)
KR (1) KR100351024B1 (fr)
CN (1) CN1175498C (fr)
AT (1) ATE322080T1 (fr)
DE (1) DE69930583T2 (fr)
MY (1) MY118019A (fr)
SG (1) SG81964A1 (fr)
TW (1) TW437078B (fr)

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TW508690B (en) * 1999-12-08 2002-11-01 Canon Kk Composite member separating method, thin film manufacturing method, and composite member separating apparatus
FR2802346B1 (fr) * 1999-12-13 2002-02-08 Upsys Probe Technology Sas Connecteur de test de haute densite d'interconnexion destine notamment a la verification de circuits integres
JP2001196566A (ja) * 2000-01-07 2001-07-19 Sony Corp 半導体基板およびその製造方法
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
FR2811807B1 (fr) * 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
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JP4803884B2 (ja) * 2001-01-31 2011-10-26 キヤノン株式会社 薄膜半導体装置の製造方法
JP4708577B2 (ja) * 2001-01-31 2011-06-22 キヤノン株式会社 薄膜半導体装置の製造方法
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
US7045878B2 (en) * 2001-05-18 2006-05-16 Reveo, Inc. Selectively bonded thin film layer and substrate layer for processing of useful devices
US6956268B2 (en) 2001-05-18 2005-10-18 Reveo, Inc. MEMS and method of manufacturing MEMS
JP2005500172A (ja) * 2001-08-15 2005-01-06 レベオ， インコーポレイティッド Ｍｅｍｓ及びｍｅｍｓ製造方法
US7163826B2 (en) 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
US6875671B2 (en) * 2001-09-12 2005-04-05 Reveo, Inc. Method of fabricating vertical integrated circuits
FR2830983B1 (fr) * 2001-10-11 2004-05-14 Commissariat Energie Atomique Procede de fabrication de couches minces contenant des microcomposants
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US7176108B2 (en) 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
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TWI242232B (en) * 2003-06-09 2005-10-21 Canon Kk Semiconductor substrate, semiconductor device, and method of manufacturing the same
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FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
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FR2858715B1 (fr) 2003-08-04 2005-12-30 Soitec Silicon On Insulator Procede de detachement de couche de semiconducteur
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
JP2005136214A (ja) * 2003-10-30 2005-05-26 Nec Corp 薄膜デバイス基板の製造方法
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US7772087B2 (en) 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
JP4771510B2 (ja) * 2004-06-23 2011-09-14 キヤノン株式会社 半導体層の製造方法及び基板の製造方法
FR2886051B1 (fr) 2005-05-20 2007-08-10 Commissariat Energie Atomique Procede de detachement d'un film mince
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
US7456080B2 (en) * 2005-12-19 2008-11-25 Corning Incorporated Semiconductor on glass insulator made using improved ion implantation process
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FR2902926B1 (fr) * 2006-06-22 2008-10-24 Commissariat Energie Atomique Procede et dispositif de suivi d'un traitement thermique d'un substrat microtechnologique.
US8148629B2 (en) * 2006-09-11 2012-04-03 Silicon China (Hk) Limited Method and structure for hydrogenation of porous monocrystalline silicon substrates
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FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
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JP5245380B2 (ja) * 2007-06-21 2013-07-24 信越半導体株式会社 Ｓｏｉウェーハの製造方法
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FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
JP2010114409A (ja) * 2008-10-10 2010-05-20 Sony Corp Ｓｏｉ基板とその製造方法、固体撮像装置とその製造方法、および撮像装置
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EP0767486A2 (fr) * 1995-10-06 1997-04-09 Canon Kabushiki Kaisha Substrat semi-conducteur et procédé de fabrication

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Also Published As

Publication number Publication date
US6597039B2 (en) 2003-07-22
EP0938129B1 (fr) 2006-03-29
ATE322080T1 (de) 2006-04-15
EP0938129A1 (fr) 1999-08-25
CN1228607A (zh) 1999-09-15
US20020093047A1 (en) 2002-07-18
DE69930583D1 (de) 2006-05-18
MY118019A (en) 2004-08-30
TW437078B (en) 2001-05-28
CN1175498C (zh) 2004-11-10
KR19990072744A (ko) 1999-09-27
US6342433B1 (en) 2002-01-29
KR100351024B1 (ko) 2002-08-30
DE69930583T2 (de) 2006-12-28

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