TW323389B - - Google Patents

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Publication number
TW323389B
TW323389B TW085112908A TW85112908A TW323389B TW 323389 B TW323389 B TW 323389B TW 085112908 A TW085112908 A TW 085112908A TW 85112908 A TW85112908 A TW 85112908A TW 323389 B TW323389 B TW 323389B
Authority
TW
Taiwan
Prior art keywords
silicon
film
silicon substrate
forming
thin film
Prior art date
Application number
TW085112908A
Other languages
English (en)
Chinese (zh)
Original Assignee
Toshiba Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Co Ltd filed Critical Toshiba Co Ltd
Application granted granted Critical
Publication of TW323389B publication Critical patent/TW323389B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
TW085112908A 1995-10-25 1996-10-22 TW323389B (2)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7276063A JPH09120965A (ja) 1995-10-25 1995-10-25 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW323389B true TW323389B (2) 1997-12-21

Family

ID=17564289

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085112908A TW323389B (2) 1995-10-25 1996-10-22

Country Status (4)

Country Link
US (1) US5874325A (2)
JP (1) JPH09120965A (2)
KR (1) KR100214766B1 (2)
TW (1) TW323389B (2)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100232898B1 (ko) * 1997-05-07 1999-12-01 김영환 반도체소자의 소자분리절연막 형성방법
JP3844566B2 (ja) * 1997-07-30 2006-11-15 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6069059A (en) * 1997-11-18 2000-05-30 Micron Technology, Inc. Well-drive anneal technique using preplacement of nitride films for enhanced field isolation
US6169011B1 (en) * 1998-03-24 2001-01-02 Sharp Laboratories Of America, Inc. Trench isolation structure and method for same
US6239003B1 (en) * 1998-06-16 2001-05-29 Texas Instruments Incorporated Method of simultaneous fabrication of isolation and gate regions in a semiconductor device
JP3338383B2 (ja) * 1998-07-30 2002-10-28 三洋電機株式会社 半導体装置の製造方法
JP2000294549A (ja) 1999-02-02 2000-10-20 Nec Corp 半導体装置及びその製造方法
GB2368464B (en) * 1999-02-02 2002-10-16 Nec Corp Semiconductor device and fabrication process therefor
JP3751469B2 (ja) * 1999-04-26 2006-03-01 沖電気工業株式会社 Ｓｏｉ構造の半導体装置の製造方法
JP2002334927A (ja) * 2001-05-11 2002-11-22 Hitachi Ltd 半導体装置の製造方法
JP2003017497A (ja) * 2001-07-04 2003-01-17 Nec Corp 半導体装置の製造方法
JP2004327489A (ja) * 2003-04-21 2004-11-18 Shin Etsu Handotai Co Ltd シリコン単結晶ウェーハ及びその製造方法
JP4015068B2 (ja) 2003-06-17 2007-11-28 株式会社東芝 半導体装置の製造方法
JP4529065B2 (ja) * 2003-08-18 2010-08-25 信越半導体株式会社 シリコン単結晶ウェーハの製造方法
JP4759948B2 (ja) * 2004-07-28 2011-08-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR100640968B1 (ko) * 2004-12-31 2006-11-02 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
JP2006196514A (ja) * 2005-01-11 2006-07-27 Nec Electronics Corp 半導体装置及びその製造方法
US7967820B2 (en) 2006-02-07 2011-06-28 P Tech, Llc. Methods and devices for trauma welding
US7737004B2 (en) * 2006-07-03 2010-06-15 Semiconductor Components Industries Llc Multilayer gettering structure for semiconductor device and method
JP5417748B2 (ja) * 2008-06-23 2014-02-19 富士通セミコンダクター株式会社 半導体装置の製造方法
JP5882579B2 (ja) * 2010-12-14 2016-03-09 キヤノン株式会社 半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1001771A (en) * 1973-01-15 1976-12-14 Fairchild Camera And Instrument Corporation Method of mos transistor manufacture and resulting structure
JPS61159741A (ja) * 1984-12-31 1986-07-19 Sony Corp 半導体装置の製造方法
NL8501992A (nl) * 1985-07-11 1987-02-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
JPS62208638A (ja) * 1986-03-07 1987-09-12 Toshiba Corp 半導体装置の製造方法
JP2666945B2 (ja) * 1988-02-08 1997-10-22 株式会社東芝 半導体装置の製造方法
US5194395A (en) * 1988-07-28 1993-03-16 Fujitsu Limited Method of producing a substrate having semiconductor-on-insulator structure with gettering sites
IT1230028B (it) * 1988-12-16 1991-09-24 Sgs Thomson Microelectronics Procedimento di fabbricazione di dispositivi semiconduttori mos avvalentesi di un trattamento "gettering" di migliorare caratteristiche, e dispositivi semiconduttori mos con esso ottenuti
JPH0719839B2 (ja) * 1989-10-18 1995-03-06 株式会社東芝 半導体基板の製造方法
JP2575545B2 (ja) * 1990-07-05 1997-01-29 株式会社東芝 半導体装置の製造方法
JPH05109736A (ja) * 1991-10-21 1993-04-30 Matsushita Electron Corp 半導体装置の製造方法
JP3024409B2 (ja) * 1992-12-25 2000-03-21 日本電気株式会社 半導体装置の製造方法
US5445975A (en) * 1994-03-07 1995-08-29 Advanced Micro Devices, Inc. Semiconductor wafer with enhanced pre-process denudation and process-induced gettering

Also Published As

Publication number Publication date
KR100214766B1 (ko) 1999-08-02
KR970024021A (ko) 1997-05-30
JPH09120965A (ja) 1997-05-06
US5874325A (en) 1999-02-23

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees