TWI809576B - 經處理的堆疊晶粒 - Google Patents

經處理的堆疊晶粒 Download PDF

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TWI809576B
TWI809576B TW110144066A TW110144066A TWI809576B TW I809576 B TWI809576 B TW I809576B TW 110144066 A TW110144066 A TW 110144066A TW 110144066 A TW110144066 A TW 110144066A TW I809576 B TWI809576 B TW I809576B
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die
microelectronic
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dielectric layer
semiconductor
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賽普里恩 艾米卡 烏佐
桂蓮 高
蘿拉 威爾 麥卡雷米
蓋爾斯 吉爾曼 方譚二世
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美商艾德亞半導體接合科技有限公司
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Abstract

技術及方法之代表性實施方案包括處理單粒化晶粒以準備接合。複數個半導體晶粒構件可自一晶圓構件單粒化，該些半導體晶粒構件各自具有實質上平坦的表面。可將材料之顆粒及碎片自該複數個半導體晶粒構件之邊緣移除。另外，該複數個半導體晶粒構件中之一或多者可經由該實質上平坦的表面接合至製備好的接合表面。

Description

經處理的堆疊晶粒
以下描述係關於積體電路（「IC」）之處理。更詳言之，以下描述係關於用於處理單粒化晶粒以準備接合之技術。 ［優先權要求及相關申請案之交叉參考］
本申請案主張在35 U.S.C. §119(e)(1)下2018年4月23日申請之美國專利申請案第15/960,179號及2017年5月11日申請之臨時申請案第62/504,834號的權益，該申請案特此以全文引用之方式併入。
晶粒可以三維配置之形式堆疊以作為各種微電子封裝方案之一部分。此可包括將一或多個晶粒層堆疊於較大基底晶粒上、將多個晶粒堆疊於豎直配置中，及該兩者之各種組合。晶粒亦可堆疊於晶圓上，或晶圓可在單粒化之前堆疊於其他晶圓上。晶粒或晶圓可使用各種接合技術而以堆疊配置之形式接合，包括使用直接介電質接合、非黏著技術，諸如ZiBond®直接接合技術或DBI®混合接合技術，該兩者可購自Invensas Bonding Technologies公司（以前為Ziptronix公司）、Xperi公司之子公司（參見例如美國專利第6,864,585號及第7,485,968號，該兩者之全文併入於本文中）。
當使用直接接合技術接合堆疊晶粒時，需要待接合之晶粒的表面極扁平且平滑。舉例而言，該些表面之表面拓樸應具有極小變化，使得該些表面可緊密地配合以形成持續結合。亦需要表面潔淨且不含雜質、顆粒及/或其他殘餘物。舉例而言，不合需要的顆粒之存在可使得接合在該些顆粒之部位處有缺陷或不可靠。舉例而言，留存於接合表面上之一些顆粒及殘餘物可在堆疊晶粒之間的接合介面處產生空隙。若空隙實質上小於金屬電互連件大小，則其可為可接受的。然而，常常不可容許造成大小接近於或超過電互連件大小之接合缺陷的顆粒，此係因為其可不利地影響互連件之電導率。
因為半導體晶圓（例如，矽晶圓）係脆性的，所以在晶粒之邊緣處產生缺陷或顆粒係常見的，此系因為晶粒被單粒化。作為一實例，矽可能在切割期間破裂，從而形成鬆散顆粒。機械切割或鋸切常常留下粗糙邊緣，且亦可將矽之顆粒或碎片留在切割晶粒之邊緣上或附近。另外，機械鋸切塊（dicing）通常將來自切塊片材之材料傳送至單粒化晶粒之側壁及邊緣。雷射切割還可將顆粒留在晶粒之表面或邊緣上。在切割之後，可使用各種程序來清潔晶粒之表面。然而，該些程序常常可將一些顆粒留在晶粒之周邊處或晶粒之邊緣壁處。即使在晶粒表面被拋光時，碎片仍然可存在於晶粒之邊緣或側壁上。被留下之鬆散顆粒及碎片在形成可靠接合時可成問題。另外，此等鬆散或部分鬆散顆粒可在後續操作中再污染所關注接合表面或接合工具等等。
可使用各種具體實例及技術來處理單粒化晶粒以準備接合。該些具體實例包含補救在晶粒上找到之缺陷之累積的技術，且包括移除、溶解或蝕刻晶粒之邊緣處的顆粒以提供平滑的接合表面。晶粒可包含半導體或非半導體材料。半導體材料可例如包含直接帶隙或間接帶隙半導體及其組合。舉例而言，非半導體材料可包含例如以下各者之介電材料：玻璃、陶瓷、玻璃陶瓷、碳化矽、碳氧化矽、氮化矽或氮氧化矽、金剛石、氧化矽等等或其組合。
一種微電子系統可包括至少一第一微電子構件，該第一微電子構件包含一基底半導體層及介電層，該介電層具有實質上平坦的表面。另外，第二微電子構件可無需黏著劑直接地接合至該第一微電子構件之該介電層，該介電層具有在該介電層之周邊處的底切，使得該介電層之面積小於該第一微電子構件及/或該第二微電子構件之佔據區的面積。替代地，該第二微電子構件可包含至少一第二基底半導體層及第二介電層，該第二介電層具有一實質上平坦的表面。另外，該第二介電層可無需黏著劑直接地接合至該第一介電層，在該第一實質上平坦的表面及該第二實質上平坦的表面處，該第一基底半導體層及該第二基底半導體層分別具有在該第一基底半導體層及該第二基底半導體層之周邊處的底切，使得該第一基底半導體層之佔據區的面積及該第二基底半導體層之一佔據區的面積小於該第一介電層及/或該第二介電層的面積。
在第一具體實例中，該第一微電子構件及/或該第二微電子構件之該基底半導體層之周邊處的底切可對應於該第一微電子構件及/或該第二微電子構件之該介電層之該周邊處的底切。
在第二具體實例中，該第二微電子構件可包括至少一基底半導體層及具有實質上平坦的表面之介電層，該第一微電子構件之該介電層直接地接合至該第二微電子構件之該介電層，且該第二微電子構件之該介電層具有在該第二微電子構件之該介電層之周邊處的底切，使得該第二微電子構件之該介電層的面積小於該第一微電子構件及/或該第二微電子構件之該佔據區的該面積。
一種用於形成微電子系統之方法可包括自晶圓構件單粒化複數個半導體晶粒構件，該些半導體晶粒構件各自具有實質上平坦的表面。可將材料之顆粒及碎片自該複數個半導體晶粒構件之邊緣移除。另外，該複數個半導體晶粒構件中之一或多者可經由該實質上平坦的表面接合至製備好的接合表面。
在第三具體實例中，可藉由蝕刻該複數個半導體晶粒構件之該些邊緣而移除材料之該些顆粒及碎片。在該複數個半導體晶粒構件處於切塊載體（諸如一切塊片材、切塊膠帶等等）上時，可蝕刻該複數個半導體晶粒構件之該些邊緣。另外，可使用化學蝕刻劑來蝕刻該複數個半導體晶粒構件之該些邊緣。在一實施方案中，該化學蝕刻劑可包含具有苯并三唑（BTA）之氫氟酸及硝酸，或抑制Cu在該蝕刻劑中溶解的其他化學物質。此外，可使用電漿蝕刻來蝕刻該複數個半導體晶粒構件之該些邊緣。另外，可蝕刻該複數個半導體晶粒構件之該些邊緣以減小該複數個半導體晶粒構件之厚度，使得在該複數個半導體晶粒構件中之每一者之該些邊緣中的一或多者處產生空間。該些半導體晶粒構件可包括氧化層以作為該實質上平坦的表面，且該蝕刻可包括移除該複數個半導體晶粒構件之該些邊緣處的該氧化層之至少一部分。再者，可蝕刻該複數個半導體晶粒構件之該實質上平坦的表面。可將該實質上平坦的表面蝕刻至預先選擇的深度或維持預先選擇的持續時間。
在第四具體實例中，在蝕刻之前，可將保護塗層塗覆至該複數個半導體晶粒構件之該實質上平坦的表面，以保護該實質上平坦的表面免受該蝕刻劑影響。
在第五具體實例中，在單粒化之後，可加熱該複數個半導體晶粒構件以使得該保護塗層自該複數個半導體晶粒構件之周邊後退。另外，可將該複數個半導體晶粒構件之該周邊蝕刻至預先選擇的深度。此外，該複數個半導體晶粒構件可包括在一基底半導體層之上的介電層。另外，可蝕刻該複數個半導體晶粒構件之該周邊以移除該介電層及曝露該複數個半導體晶粒構件之該周邊處的該基底半導體層。
在第六具體實例中，可藉由一直接接合技術或金屬至金屬擴散接合而無需黏著劑來接合該複數個半導體晶粒構件中之該一或多者。
在第七具體實例中，可將材料之顆粒及碎片自該複數個半導體晶粒構件之側壁移除，其中藉由蝕刻該複數個半導體晶粒構件之該側壁而將該些顆粒及碎片自該側壁移除。
在一個具體實例中，在單粒化步驟之後，可藉助於一或多種鹼性流體中之超音波或超高頻音波輻射而將材料之顆粒及碎片自晶粒之側壁移除。在粒子移除之後，可進一步蝕刻晶粒之側壁以移除側壁之部分及晶粒之平坦介電層的部分。
可使用方塊流程圖說明所揭示之程序中的一些，包括圖形流程圖及/或本文流程圖。並非意欲將描述所揭示之程序的次序視為限制，且可以任何次序組合任何數目個所描述之程序區塊以實施該些程序或替代程序。另外，可在不脫離本文中所描述之主題之精神及範圍的情況下自程序刪除個別區塊。此外，在不脫離本文中所描述之主題的範圍之情況下，所揭示程序可在任何合適之製造或處理裝置或系統，以及任何硬體、軟體、韌體或其組合中實施。
在下文使用複數個實例來更詳細地解釋實施方案。儘管在此處且在下文論述各種實施方案及實例，但另外實施方案及實例可藉由組合個別實施方案及實例之特徵及元件來成為可能。概述
可使用各種具體實例及技術來處理單粒化晶粒以準備接合。該些具體實例包含補救在晶粒上找到之顆粒之累積的技術，該些顆粒包括在晶粒之單粒化期間產生的顆粒，且包括移除、溶解或蝕刻晶粒之邊緣處的碎片以提供平滑的接合表面。
圖1的（A）係根據一具體實例之展示晶粒之頂部表面上之缺陷的剖面圖。如所示，展示第一晶粒102不具有任何缺陷。與此對比，展示第二晶粒104具有缺陷106。當然，應瞭解，缺陷106可出現在第一晶粒102及/或第二晶粒104之任何表面、側壁及/或邊緣上。
可自晶圓單粒化及/或移除第一晶粒102及/或第二晶粒104，該些晶圓諸如GaAs、經金剛石塗佈基板、碳化矽、氧化矽、氮化矽、矽晶圓、鈮酸鋰、鉭酸鋰、扁平面板、玻璃、陶瓷、電路板、封裝體、插入件、具有或不具有嵌入式金屬層之結構、導電互連件108、一或多個器件等等。在一個具體實例中，缺陷106可包括顆粒及/或碎片，且可由對第一晶粒102及/或第二晶粒104進行晶粒切割、切塊及/或單粒化引起。舉例而言，第一晶粒102及/或第二晶粒104之機械切割（亦即，鋸切）可造成諸如顆粒106之缺陷，特別是在邊緣及/或側壁處。另外，當切割（甚至使用雷射）第一晶粒102及/或第二晶粒104時，第一晶粒102及/或第二晶粒104可破裂及/或產生顆粒106（諸如氧化矽顆粒）。此外，在拋光第一晶粒102及/或第二晶粒104之後，顆粒106之碎片仍然可存在於第一晶粒102及/或第二晶粒104之邊緣及/或側壁上。
圖1的（B）係展示具有諸如顆粒106之缺陷之接合晶粒之區段的剖面圖。如所示，在缺陷106存在於第二晶粒104之接合表面的一部分處的情況下，第一晶粒102無法充分地接合至第二晶粒104。此係由在第一晶粒102與第二晶粒104之間找到的間隙110（或空隙）展示。在接合完整性受損的情況下，或在間隙110足夠大以不利地影響配對導電互連件108（若存在於晶粒102及104之接合表面處）之電導率的情況下，此間隙110可不能忍受。如上文所論述，儘管可在第二晶粒104之接合表面上找到缺陷106，但可沿著第一晶粒102及/或第二晶粒104之另一表面及/或側壁找到額外或其他缺陷（諸如顆粒）。
圖1的（C）係展示不具有缺陷之緊密接合晶粒之區段的剖面圖。如所示，第一晶粒102充分地且完全地接合至第二晶粒104。在晶粒102及104之表面處的任何導電互連件108之間存在可靠電導率的情況下，該些導電互連件108亦會接合。圖1的（C）展示在第一晶粒102及第二晶粒104中之每一者已被恰當地製備以用於接合之後的第一晶粒102及第二晶粒104。舉例而言，可清潔及蝕刻第一晶粒102及/或第二晶粒104之邊緣及側壁，以移除矽之顆粒及碎片。可運用乾式（電漿）蝕刻及/或濕式（化學）蝕刻來蝕刻第一晶粒102及/或第二晶粒104之邊緣，而在單粒化之後，第一晶粒102及/或第二晶粒104仍然存在於載體（例如，切塊片材或膠帶、夾環等等）上。可將保護塗層塗覆至第一晶粒102及/或第二晶粒104之接合表面，以在單粒化及蝕刻期間保護該表面。在一個實例中，可蝕刻第一晶粒102及/或第二晶粒104之表面及側壁，而在另一實例中，該蝕刻可限於第一晶粒102及/或第二晶粒104之側壁。應注意，簡單地且未按比例展示導電互連件108。舉例而言，導電互連件108可包含共同形成導電互連件108之一或多個層。此外，導電互連件108可部分地或完全地延伸穿過晶粒102及104中之任一者或兩者，或甚至可僅提供於晶粒102及104之表面處或沿著晶粒102及104之表面提供以作為晶粒102及104內之痕跡互連器件的圖案。實例具體實例
圖2說明根據一具體實例之處理堆疊晶粒之實例程序200。在（A）處，基板202（其可為例如矽晶圓）可包括接合層204，接合層204可包含諸如氧化物之絕緣體或介電層，或混合接合層，例如，絕緣材料（諸如氧化物）與導電互連層之組合。此接合層204可形成於基板202之一側或兩側上。接合層204可受第一保護層206及/或第二保護層208保護。替代地，基板202可能會曝露及/或具有任何數目個保護層。
在（B）處，基板202可在載體212上單粒化成複數個單粒化晶粒210。在一個具體實例中，載體212可包括處理片材、切塊片材或膠帶、夾環等等。另外，可使用鋸切塊、濕式蝕刻或乾式蝕刻或雷射方法或其組合來單粒化基板202。在一個具體實例中，單粒化晶粒210可具有實質上平坦的表面。
在（C）處，單粒化晶粒210可曝露於紫外線光（UV）（例如，以固化用作基板202之載體212之膠帶上的黏著層、減小接觸膠帶之晶粒210表面之間的黏著等等）。另外，在一個具體實例中，在準備清潔並進一步處理單粒化晶粒210時，當單粒化晶粒210係在載體212上時，載體212可延展。舉例而言，進一步處理可包括減小單粒化晶粒210之厚度。
在（D）處，可清潔單粒化晶粒210，且可蝕刻單粒化晶粒210之側壁。舉例而言，清潔可移除一或多個保護層，包括第一保護層206及/或第二保護層208。在一具體實例中，蝕刻可溶解氧化矽、氮化矽及/或矽以消除顆粒及/或碎片。化學蝕刻劑211（包括酸）可用以蝕刻晶粒210之表面的周邊，包括接合層204，且亦可用以蝕刻單粒化晶粒210之側壁。在蝕刻單粒化晶粒210之表面及/或側壁的一實例中（例如，對於矽晶粒210），化學蝕刻劑211可包含氫氟酸與合適氧化劑之化學混合物，例如硝酸。在一些應用中，濕蝕刻劑可包含緩衝氫氟酸與合適有機酸以及氧化劑之混合物。在其他應用中，可將合適金屬錯合劑添加至蝕刻溶液以保護晶粒210接合表面上之金屬免受蝕刻劑影響。在一個實例中，金屬錯合或鈍化劑可包含具有三唑部分之分子，例如苯并三唑（BTA）等等。在一個具體實例中，BTA可保護單粒化晶粒210之表面上的銅免受蝕刻溶液侵蝕或溶解影響。
在蝕刻晶粒210之表面（及側壁）及剝去第一保護層206及/或第二保護層208之後，自晶粒210之接合表面清潔錯合劑。作為濕式蝕刻之替代例，亦可使用乾式蝕刻方法來清潔晶粒210之側壁，包括使用與用於蝕刻矽中之程序相似的電漿處理。在乾式側壁蝕刻步驟之後，可自晶粒210之側壁的接合表面剝離第一保護層206。清潔第一保護層206亦可包括清潔由乾式蝕刻產生之任何有機材料殘餘物。在一個具體實例中，可使經處理的晶粒210之側壁上的有機殘餘物完好。牢固黏著之側壁有機殘餘物可最小化自晶粒210脫落之後續顆粒。
另外，單粒化晶粒210之清潔及/或進一步處理可在旋塗夾具214（等等）上進行。化學蝕刻劑211被噴射至經切塊晶圓表面上且在晶粒210之頂部表面之上形成薄層，並且填充晶粒210之間的間隙。在一個具體實例中，蝕刻單粒化晶粒210之側壁可致使移除晶粒210之側壁上的缺陷。
視情況，在一具體實例中，可選擇性地塗佈晶粒210之側壁以塗佈側壁及可能存在於側壁上之任何顆粒及/或碎片。舉例而言，可使用旋塗程序、電塗程序等等將選擇性塗層218塗覆至側壁。將顆粒及/或碎片塗佈至具有塗層218之側壁以將顆粒及/或碎片黏著至側壁，從而防止顆粒及/或碎片污染晶粒210之其他區域，包括晶粒210之接合表面。在各種具體實例中，塗層218包含黏著至側壁之矽且通常不會黏著至任何其他表面的材料，諸如玻璃、硼摻雜玻璃、磷摻雜玻璃等等。
在各種具體實例中，塗層218包含大致為50 nm或小於50 nm之層，其將顆粒及碎片截獲至晶粒210之側壁且防止顆粒及碎片自側壁脫落。可將塗層218熱固化至晶粒210，以在預定義溫度（例如，大致為80℃等等）下穩定預定義持續時間。雖然可在如所論述之清潔晶粒210之後添加塗層218，但在各種具體實例中，在程序200中之其他步驟處，可將塗層218沈積至側壁。
在（E）處，單粒化晶粒210可經歷電漿程序（諸如灰化）以移除第一保護層206之任何殘餘物。在（F）處，可清潔單粒化晶粒210以移除由步驟（E）產生之殘渣之任何殘餘物或顆粒。在（G）處，可將單粒化晶粒210（包括接合層204中之一者或兩者）電漿活化（表面活化）以使單粒化晶粒210準備直接接合。在（H）處，可清潔經電漿活化單粒化晶粒210。在（I）處，單粒化晶粒210中之一或多者可接合至第二基板216之製備好的表面。詳言之，單粒化晶粒210之接合層204（例如，具有或不具有導電層之氧化層或介電層）可直接接合至第二基板216之製備好的表面。在一個具體實例中，單粒化晶粒210（經由接合層204）可使用ZIBOND®直接接合或DBI®混合接合、技術等等接合至第二基板216，其中單粒化晶粒210直接接合（且在一些情況下，電連接）至第二基板216之表面的部分而無需使用黏著劑。
在各種實施方案中，第二基板216可包含以下各者之另一製備好的表面：矽晶圓、GaAs、金剛石塗佈基板、碳化矽、氧化矽、氮化矽、鈮酸鋰、鉭酸鋰、平板、玻璃、陶瓷、電路板、封裝體、插入件、具有或不具有嵌入式器件之結構等等。在一個具體實例中，製備好的第二基板216包含另一晶粒210或另一接合晶粒304之表面，如下文進一步論述。
圖3說明根據一具體實例之處理堆疊晶粒之實例程序300。如上文所描述，程序300之步驟（A）至（D）以與程序200之步驟（A）至（D）一致的方式起作用。此包括蝕刻晶粒210之表面及周邊（在相同或單獨的程序步驟中）以移除來自晶粒210之表面及周邊的矽或氧化物的顆粒及碎片。
視情況，在一具體實例中，可選擇性地塗佈晶粒210之側壁以塗佈側壁及可能存在於側壁上之任何顆粒及/或碎片，如上文所描述。舉例而言，可使用旋塗程序、電塗程序等等將選擇性塗層218塗覆至側壁。將顆粒及/或碎片塗佈至具有塗層218之側壁以將顆粒及/或碎片黏著至側壁，從而防止顆粒及/或碎片污染晶粒210之其他區域，包括晶粒210之接合表面。在各種具體實例中，塗層218包含黏著至側壁之矽且通常不會黏著至任何其他表面的材料，諸如玻璃、硼摻雜玻璃、磷摻雜玻璃等等。
在各種具體實例中，塗層218包含大致為50 nm或小於50 nm之層，其將顆粒及碎片截獲至晶粒210之側壁且防止顆粒及碎片自側壁脫落。可將塗層218熱固化至晶粒210，以在預定義溫度（例如，大致為80℃等等）下穩定預定義持續時間。雖然可在如所論述之清潔晶粒210之後添加塗層218，但在各種具體實例中，在程序300中之其他步驟處，可將塗層218沈積至側壁。
繼續參看程序300，在（E）處，針對所描述之程序步驟中之全部（在一些具體實例中，包括單粒化），可將單粒化晶粒210轉移至旋塗夾具214（等等），且當單粒化晶粒210在單一載體（諸如旋塗夾具214等等）上時進行處理/清潔。替代地，針對每一站處的一或多個程序，可在不同載體（諸如旋塗板302）之間轉移單粒化晶粒210。在（F）處，單粒化晶粒210可經歷電漿處理，以在仍然處於旋塗板302上時移除第一保護層206之任何殘餘物（以程序200之步驟（E）相似的方式）。
在（G）處，可清潔單粒化晶粒210以移除由（F）處之電漿程序產生的殘餘物。在（H）處，可將單粒化晶粒210電漿活化（表面活化）以使單粒化晶粒210（包括接合層204）準備直接接合。在（I）處，可清潔經電漿活化單粒化晶粒210。
在（J）處，單粒化晶粒210中之一或多者可接合至第二基板216之製備好的表面。詳言之，接合層204（例如，具有或不具有導電層之氧化層或介電層）可接合至第二基板216之製備好的表面。在一個具體實例中，單粒化晶粒210（經由接合層204）可使用ZIBOND®直接接合或DBI®混合接合、技術等等直接接合至第二基板216（例如，無需黏著或介入層）。
在（K）處，一或多個額外單粒化晶粒304（其相似於單粒化晶粒210（例如，晶粒304亦可自基板202單粒化）而製備）可接合至單粒化晶粒210中之一或多者的經曝露第二表面，從而形成一或多個晶粒堆疊。詳言之，單粒化晶粒304之接合層306（例如，具有或不具有導電層之氧化層或介電層）可直接接合至單粒化晶粒210之第二表面，單粒化晶粒210亦已製備用於接合。準備接合可按需要包括一或多個清潔、表面平坦化及電漿處理程序步驟。另外，亦可蝕刻晶粒210之第二表面（包括周邊）以移除不合需要的顆粒及碎片等等。
可以相同方式添加額外單粒化晶粒304以與所要量之晶粒層形成晶粒堆疊。在一些具體實例中，可在接合之後對單粒化晶粒210及第二基板216熱處理，其中在每一單粒化晶粒304層之後添加額外熱處理。替代地，一旦若干或所有堆疊晶粒（210、304）層處於適當位置且接合，就對單粒化晶粒210、單粒化晶粒304及第二基板216熱處理。
圖4說明根據一具體實例之處理堆疊晶粒的另一實例程序400。在（A）處，將抗蝕劑層402塗佈於單粒化晶粒210上，單粒化晶粒210包括接合層204（例如，具有或不具有導電層或結構之絕緣層或介電層）及基板區202（例如，矽）。在一實施方案中，可圖案化抗蝕劑層402，例如以曝露單粒化晶粒210之周邊，同時保護單粒化晶粒210之表面的其餘部分。在各種具體實例中，可使用切塊及/或劃線來使單粒化晶粒210單粒化。
在（B）處，可清潔及蝕刻單粒化晶粒210之經曝露邊緣及側壁，從而在單粒化晶粒210之周邊處產生底切或凹口。舉例而言，可藉由蝕刻而使單粒化晶粒210之粗糙切割邊緣平滑。另外，可使單粒化晶粒210之周邊凹進，以使單粒化晶粒210在周邊處之總厚度縮減，從而在單粒化晶粒210之邊緣處產生空間。舉例而言，可蝕刻具有基板202上之接合層204（例如，介電質、氧化物等等）的單粒化晶粒210以移除單粒化晶粒210之周邊處的接合層204之氧化物中的一些，及在一些狀況下，亦移除基板202之矽的一部分。該蝕刻使得接合層204之介電氧化物自單粒化晶粒210之邊緣反向凹進，從而曝露凹口下方基板202之矽。在一個具體實例中，由凹口形成之空間可考慮到在直接接合期間接合表面之某容差，以改良直接接合技術之可靠性且移除來自接合之應力。
在一個具體實例中，可在升高溫度（例如，120℃）下處理單粒化晶粒210，使得安置於接合層204上之抗蝕劑層402自單粒化晶粒210之邊緣流動且撤回。當蝕刻單粒化晶粒210之邊緣時，可移除接合層204之經曝露部分。另外，取決於用於蝕刻之持續時間及處方集，可另外移除基板202之矽中的一些。舉例而言，持續時間愈長，可移除愈大量之基板202。在一些狀況下，由於單粒化晶粒210之蝕刻，接合層204可具有傾斜剖面。在執行蝕刻至基板202之深度的情況下，此傾斜剖面可延伸至基板202（例如，矽）中。
在一些具體實例中，可視需要使用微影方法以及乾式蝕刻、濕式蝕刻或該兩者來執行回蝕接合層204之程序。舉例而言，可圖案化晶粒210之表面，及藉由乾式蝕刻方法移除之接合層204的非想要部分，以及藉由濕式蝕刻方法移除之任何非想要曝露導電特徵。在其他應用中，在單段操作中移除非想要介電質及導電部分可為較佳的。在一個實例中，可將含有鹵素離子之濕蝕刻劑（例如，緩衝氫氟酸及含有可使導電特徵氧化之過氧化氫或硝酸（等等）的處方集）塗覆至晶粒210之表面以移除非想要介電質及導電特徵。在移除非想要介電質及導電特徵之後，可塗覆保護層以用於單粒化操作。
在（C）處，可自單粒化晶粒210之表面移除抗蝕劑層402。另外，在（D）處，可清潔單粒化晶粒210。
在（E）及（F）處，單粒化晶粒210可接合至基板404（諸如另一晶粒210或304、第二基板216等等），基板404已準備接合，如上文所論述。在一個具體實例中，單粒化晶粒210可使用ZIBOND®或混合DBI®技術等等（例如，無需黏著或介入層）接合至基板404之製備好的表面。在（E）及（F）處對圖4之說明中，晶粒210僅展示具有接合層204。然而，在一些具體實例中，待接合之兩個構件（例如，晶粒210、晶粒304或第二基板216）可包括接合表面處之氧化區（諸如接合層204）。換言之，該些構件在各別氧化區處接合。在一些應用中，晶粒210及基板202之製備好的表面之接合層204可包括導電特徵（圖中未示）。晶粒210及基板202之製備好的表面之介電部分可首先在較低溫度下接合。任何導電特徵可在介於150℃至350℃之間的較高溫度下接合。在其他應用中，介電部分及導電特徵接合在相同溫度下形成。
在（E）處所示之實施方案中，由於步驟（D）之蝕刻，單粒化晶粒210之接合層204的邊緣可包括底切408。在該實施方案中，單粒化晶粒210可包括單粒化晶粒210之周邊處的底切408，使得接合層204之面積小於基板202及/或基板404之佔據區的面積。另外或替代地，在（F）處所示之實施方案中，由於步驟（D）之蝕刻，基板202及基板404之邊緣可包括底切410。在此實施方案中，單粒化晶粒210可包括單粒化晶粒210之周邊處的底切410，使得接合層204之面積大於基板202及/或基板404之佔據區的面積。在該實施方案中，基板202及基板404可分別與第一及第二經接合微電子構件相對應。
根據各種具體實例，本文中所描述之邊緣或側壁蝕刻技術可降低用於高量製造單粒化晶粒210之直接接合程序的複雜度及成本。另外，自單粒化晶粒210之周邊及/或邊緣移除切塊顆粒及碎片可縮減晶圓間、晶粒至晶圓、晶粒間及晶粒至系統封裝中之程序相關缺陷。此外，藉由使堆疊式單粒化晶粒210之邊緣圓化，可縮減以三維配置形式堆疊之經封裝單粒化晶粒210中的應力。本文中所描述之技術亦可引起用於較少ZiBond®及直接接合互連（DBI®）製造器件之晶粒處理步驟、較高製造產出率及改良式利潤邊際。所揭示技術之其他優點對於熟習此項技術者亦將係顯而易見的。
圖5的（A）係根據一具體實例之具有凹進接合層204（例如，具有或不具有導電層之絕緣或介電層）的實例晶粒210之一部分的剖面圖。另外，圖5的（B）係具有凹進接合層204（例如，氧化區）之晶粒210之剖面圖的放大視圖。如所示，晶粒210可包括自基板202反向凹進之接合層204。舉例而言，圖5的（B）之剖面圖可與圖4之步驟（D）中所示的剖面圖相對應。另外，圖5的（B）包括接合層204之一側上的凹口，然而，如圖4之步驟（D）中及圖5的（C）處所示，凹口亦可位於接合層204之兩側（或其他側）。
詳言之，由於蝕刻，接合層204之傾斜剖面502可延伸至基板202中（例如，如參考圖4之步驟（D）所描述）。另外，甚至在基板202之周邊處存在任何顆粒的情況下，傾斜剖面502可提供基板202之外圍處的間隙，使得可在例如單粒化晶粒210與第二基板216之製備好的表面（等等）之間達成密切且緊密的接合。
舉例而言，此在圖5的（C）中進行說明，其中將實例晶粒210示出接合至另一實例晶粒210'，從而形成實例晶粒堆疊或實例微電子總成500（等等）。如對圖5的（C）之說明中所示，接合層204（其包括諸如氧化物之絕緣或介電材料且亦可包括一或多個導電層或結構504）直接接合至接合層204'（其亦包括諸如氧化物之絕緣或介電材料且亦可包括一或多個導電層或結構504'）。導電特徵504及504'可僅延伸至各別接合層204及204'中或可部分地或完全延伸穿過晶粒201及210'。接合層204處之凹口及接合層204'（若存在）處之凹口可在微電子總成500之周邊處形成間隙506，其中晶粒210接合至晶粒210'。在各種具體實例中，間隙506之大小可使得間隙506中殘留的任何顆粒508可能不會妨礙在接合層204與204'之間形成密切且緊密的接合，包括導電結構504與504'之間密切且導電可靠的接合。在各種具體實例中，可按需要例如用囊封物、介電材料、底填充材料等等來填充間隙506。在其他具體實例中，間隙506可保持未填充，或可按需要用其他惰性或活性材料填充。如圖5的（A）及圖5的（B）中所示之相似剖面可在晶粒210及210'之背側上產生，且多於兩個晶粒可堆疊在一起。
圖6係根據一具體實例之說明用於處理堆疊晶粒之實例程序的流程圖600。在602處，程序包括自晶圓構件（諸如基板202）單粒化複數個半導體晶粒構件（諸如單粒化晶粒210或單粒化晶粒304））。在一具體實例中，該些半導體晶粒構件中之每一者具有實質上平坦的表面。在另一具體實例中，程序包括將保護塗層（諸如第一保護層206）沈積於半導體晶粒構件之實質上平坦的表面之上（在單粒化之前抑或之後）。
在一個具體實例中，程序包括在單粒化之後，加熱複數個半導體晶粒構件以使得保護塗層（諸如第一保護層206）自複數個半導體晶粒構件之周邊後退。另外，可將複數個半導體晶粒構件之周邊及/或複數個半導體晶粒構件之實質上平坦的表面蝕刻至預先選擇之深度。
替代地，複數個半導體晶粒構件可包括在基底半導體層之上的介電層。另外，介電層可具有實質上平坦的表面，且如上文所描述，介電層可包括一或多個導電特徵。在一個具體實例中，程序包括蝕刻複數個半導體晶粒構件之周邊，使得移除介電層之至少一部分且曝露複數個半導體晶粒構件之周邊處的基底半導體層。
在604處，程序包括將材料之顆粒及碎片自複數個半導體晶粒構件之邊緣移除。替代地，可將顆粒及碎片自複數個半導體晶粒構件之側壁移除。在一個具體實例中，可藉由蝕刻複數個半導體晶粒構件之邊緣及/或側壁而移除顆粒及碎片。視情況，在複數個半導體晶粒構件處於切塊載體上時，進行對邊緣及/或側壁之蝕刻。另外，該蝕刻可使用電漿蝕刻及/或化學蝕刻劑，化學蝕刻劑包含具有苯并三唑（BTA）之氫氟酸及硝酸。在一替代實施方案中，可將保護塗層（諸如第一保護層206）塗覆至複數個半導體晶粒構件之實質上平坦的表面以保護實質上平坦的表面免受蝕刻劑影響。
在606處，程序包括經由實質上平坦的表面而將複數個半導體晶粒構件中之一或多者接合至製備好的接合表面。舉例而言，可使用ZIBOND®或DBI®接合技術等等藉由直接接合進行接合而無需黏著或介入層。接合可包括在晶粒之接合表面及製備好的接合表面處電耦合相對的導電特徵。
使用方塊流程圖說明本文中所描述之所揭示程序。並非意欲將描述所揭示之程序的次序視為限制，且可以任何次序組合任何數目個所描述之程序區塊以實施該些程序或替代程序。另外，可在不脫離本文中所描述之主題之精神及範圍的情況下自程序刪除個別區塊。此外，在不脫離本文中所描述之主題的範圍之情況下，所揭示程序可在任何合適之製造或處理裝置或系統，以及任何硬體、軟體、韌體或其組合中實施。
儘管本文中論述了各種實施方案及實例，但藉由組合個別實施方案及實例之特徵及元件，另外實施方案及實例可為可能的。結論
儘管已以特定針對於結構特徵及/或方法行動之語言描述本發明之實施方案，但應理解，實施方案不一定限於所描述之特定特徵或行動。確切而言，將特定特徵及行動揭示為實施實例器件及技術之代表性形式。
本文之每項技術方案構成單獨具體實例，且組合不同技術方案及/或不同具體實例之具體實例在本發明之範圍內，且將在查閱本發明之後即刻對於一般熟習此項技術者顯而易見。
102:第一晶粒 104:第二晶粒 106:缺陷/顆粒 108:導電互連件 110:間隙 200:程序 202:基板/基板區 204:接合層 204':接合層 206:第一保護層 208:第二保護層 210:晶粒 210':晶粒 211:化學蝕刻劑 212:載體 214:旋塗夾具 216:第二基板 218:塗層 300:程序 302:旋塗板 304:晶粒 306:接合層 400:程序 402:抗蝕劑層 404:基板 408:底切 410:底切 500:微電子總成 502:傾斜剖面 504:導電層或結構/導電特徵 504':導電層或結構/導電特徵 506:間隙 508:顆粒 600:流程圖 602:步驟 604:步驟 606:步驟
參考附圖闡述詳細描述。在該些圖中，參考編號之最左側數位識別首次出現該參考編號之圖。在不同圖中使用相同參考編號指示相似或相同物件。 對此論述，在圖中所說明之器件及系統展示為具有大量構件。如本文中所描述，器件及/或系統之各種實施方案可包括更少構件且保持在本發明之範圍內。替代地，器件及/或系統之其他實施方案可包括額外構件或所描述構件之各種組合，且保持在本發明之範圍內。 [圖1]的（A）係根據一具體實例之展示晶粒之頂部表面上之缺陷的剖面圖。圖1的（B）係展示具有缺陷之接合晶粒之區段的剖面圖。圖1的（C）係展示不具有缺陷之接合晶粒之區段的剖面圖。 [圖2]係根據一具體實例之說明處理堆疊晶粒之實例程序的圖形流程圖。 [圖3]係根據另一具體實例之說明處理堆疊晶粒之實例程序的圖形流程圖。 [圖4]係根據另外具體實例之說明處理堆疊晶粒之實例程序的圖形流程圖。 [圖5]的（A）係根據一具體實例之具有凹進氧化區之晶粒的剖面圖。圖5的（B）係具有凹進氧化區之晶粒之剖面圖的放大視圖。圖5的（C）係具有凹進氧化區之接合晶粒配置的實例。 [圖6]係根據一具體實例之說明用於處理堆疊晶粒之實例程序的流程圖。
200:程序
202:基板/基板區
204:接合層
206:第一保護層
208:第二保護層
210:晶粒
211:化學蝕刻劑
212:載體
214:旋塗夾具
216:第二基板
218:塗層

Claims (33)

  1. 一種微電子系統，其包含：第一微電子構件，其包含第一半導體層和第一介電層，所述第一介電層具有第一實質上平坦的表面；晶粒，其包含第二半導體層和第二介電層，所述第二介電層具有第二實質上平坦的表面，其中所述第二介電層的一部分在所述第二介電層的周邊處凹陷，使得所述第二介電層之所述第二實質上平坦的表面的面積小於所述晶粒的最寬部分的橫截面面積；以及其中所述第二介電層直接地接合至所述第一介電層而無黏著劑。
  2. 如請求項1之微電子系統，其中所述第二介電層在所述第一微電子構件和所述晶粒之間產生底切。
  3. 如請求項2之微電子系統，其中所述底切延伸至所述第二半導體層中，使得所述第二半導體層暴露在所述晶粒的周邊處。
  4. 如請求項1之微電子系統，其中所述第二介電層包括實質上平坦的氧化層，並且其中在所述第二介電層的一個或多個邊緣處的所述實質上平坦的氧化層的至少一部分被凹陷或移除。
  5. 如請求項1之微電子系統，其中所述第二半導體層具有底切，所述底切包括對應於所述第二介電層的凹陷部分之所述第二半導體層的周邊處的凹陷。
  6. 如請求項1之微電子系統，其中所述第一介電層的一部分在所述第一介電層的周邊處凹陷，使得所述第一介電層的表面之面積小於所述第一微電子構件的最寬部分的橫截面面積。
  7. 如請求項1之微電子系統，其進一步包含在所述第一半導體層的周邊處之底切、在所述第二半導體層的周邊處之底切、或在所述第一半導體 層的周邊處之底切以及在所述第二半導體層的周邊處之底切。
  8. 如請求項1之微電子系統，其中所述第一微電子構件或所述晶粒包括直接帶隙或間接帶隙半導體。
  9. 如請求項1之微電子系統，其中所述第一微電子構件包括晶圓。
  10. 如請求項1之微電子系統，其中所述第二介電層包括傾斜剖面。
  11. 如請求項10之微電子系統，其中所述傾斜剖面延伸至所述第二半導體層。
  12. 如請求項1之微電子系統，其中所述第二介電層的凹陷部分以介電材料填充。
  13. 如請求項12之微電子系統，其中所述介電材料包括氧化矽。
  14. 如請求項1之微電子系統，其中所述第二介電層的凹陷部分以囊封物填充。
  15. 如請求項1之微電子系統，其中所述晶粒由所述第二半導體層和所述第二介電層組成。
  16. 如請求項10之微電子系統，其中所述傾斜剖面實質上延伸所述周邊的整個。
  17. 如請求項10之微電子系統，其中所述傾斜剖面包括經蝕刻的表面。
  18. 如請求項17之微電子系統，其中所述經蝕刻的表面實質上沒有任何碎片和顆粒。
  19. 一種微電子系統，其包含：第一晶粒構件，其包括在第一基底半導體層上方的第一介電層，所述介電 層具有實質上平坦的表面；第二微電子構件，其包括第二介電層和第二基底半導體層，其中所述第二介電層直接地接合到所述第一介電層而無需黏著劑；以及其中所述第一晶粒構件的周邊和所述第二基底半導體層的周邊是凹陷的，使得所述第一晶粒構件的佔據區的面積和所述第二基底半導體層的佔據區的面積均小於所述第一介電層的面積或所述第二介電層的面積中的至少一個。
  20. 如請求項19之微電子系統，其中所述第一介電層之面積小於所述第一基底半導體層之面積。
  21. 如請求項19之微電子系統，其中所述第一介電層的至少一部分在所述第一晶粒構件的所述周邊處凹陷。
  22. 如請求項19之微電子系統，其中所述第一基底半導體層的至少一部分在所述第一晶粒構件的所述周邊處凹陷。
  23. 如請求項19之微電子系統，其中所述第二微電子構件的周邊在所述第一晶粒構件的接合介面處凹陷。
  24. 一種微電子總成，其包含：半導體晶粒，其包括至少一第一平坦的介電層，所述第一平坦的介電層在所述半導體晶粒的周邊處具有凹陷；以及微電子構件，其包括第二平坦的介電層，其中所述第一平坦的介電層直接地接合至所述第二平坦的介電層；以及其中所述凹陷包括傾斜剖面。
  25. 如請求項24之微電子總成，其中所述微電子構件具有底切，所述底切包括在所述微電子構件的周邊處之凹陷。
  26. 如請求項24之微電子總成，其中所述第一平坦的介電層包括氧化層，以作為與所述微電子構件的接合表面，其中所述氧化層的一個或多個 邊緣凹陷或移除並且暴露在所述氧化層下方的基底層。
  27. 如請求項24之微電子總成，其中所述半導體晶粒以及所述微電子構件中的至少一個包括直接帶隙或間接帶隙半導體。
  28. 如請求項24之微電子總成，其中所述半導體晶粒以及所述微電子構件中的至少一個進一步包括非半導體材料。
  29. 如請求項24之微電子總成，其中所述半導體晶粒以及所述微電子構件各自包括微電子晶粒。
  30. 如請求項24之微電子總成，其中所述第二平坦的介電層在所述微電子構件的周邊處具有凹陷。
  31. 如請求項24之微電子總成，其中所述傾斜剖面延伸至所述半導體晶粒的半導體層。
  32. 如請求項24之微電子總成，其中所述傾斜剖面包括經蝕刻的表面。
  33. 如請求項32之微電子總成，其中所述經蝕刻的表面實質上沒有任何碎片和顆粒。
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