US6383938B2 - Method of anisotropic etching of substrates - Google Patents

Method of anisotropic etching of substrates Download PDF

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Publication number
US6383938B2
US6383938B2 US09/295,100 US29510099A US6383938B2 US 6383938 B2 US6383938 B2 US 6383938B2 US 29510099 A US29510099 A US 29510099A US 6383938 B2 US6383938 B2 US 6383938B2
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Prior art keywords
etching
substrate
etching process
chamber
passivating
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Expired - Lifetime
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US09/295,100
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US20010044213A1 (en
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Tamarak Pandhumsoporn
Kevin Yu
Michael Feldbaum
Michel Puech
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WSOU Investments LLC
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Alcatel SA
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Priority to AT00400462T priority patent/ATE341099T1/de
Priority to EP00400462A priority patent/EP1047122B1/de
Priority to DE60030905T priority patent/DE60030905T2/de
Priority to JP2000055248A priority patent/JP4601113B2/ja
Publication of US20010044213A1 publication Critical patent/US20010044213A1/en
Publication of US6383938B2 publication Critical patent/US6383938B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H10P50/244—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials comprising alternated and repeated etching and passivation steps

Definitions

  • the invention relates to a method of anisotropic plasma etching of substrates preferably defined with an etching mask in which the etch rate and selectivity is increased.
  • the method can be well implemented for manufacturing microelectromechanical system (MEMS), as well as microelectronic devices.
  • MEMS microelectromechanical system
  • Anisotropic plasma etching can work independent of crystal orientation of the substrate or doping level. This method also applies to doped or undoped polysilicon.
  • Preferred fields of applications are MEMS technology, where structures have a high aspect ratio, i.e., a high structural height to width ratio.
  • Other examples include surface wave technology, where narrow grooves and vertical walls are etched to produce actuators, surface wave filters, delay lines, etc.
  • Additional microelectronics applications include storage cells, insulation, collector contacts, etc.
  • RIE Reactive Ion Etching
  • relatively high energy ions ⁇ 100 eV
  • reactive halogens such as fluorine, chlorine or bromine
  • fluorine, chlorine or bromine reactive halogens
  • the resulting ion bombardment of the etching ground i.e., the area to be etched, initiates the reaction of the radicals with the silicon to be depleted.
  • the etching of the sidewalls is minimal due to the directionality of the ions.
  • U.S. Pat. No. 5,501,893 discloses an etching method that includes alternating etching and polymerizing steps where the purpose of the polymerizing step is to provide a polymer layer on the surfaces that were exposed in the previous etching step to form a temporary etch stop. Thus the side walls are protected from etching during the etching steps.
  • the gas mixtures introduced during the etching and polymerizing steps are different such that different gas mixtures are cycled during the respective etching and polymerizing steps.
  • the gas mixture includes SF 2 and Ar and in the polymerizing step the gas mixture includes CHF 3 and Ar.
  • the problem with cycling different gases is that the time ratio of the etch deposition cycle depends on the speed of the gas mixtures and varies from point to point, affecting the uniformity. Also, the time for species to arrive at the bottom of the etched trench varies drastically for trenches having different sized openings. Also, this method typically requires more complex hardware and controls to introduce the two different gas mixtures in cycles.
  • the object of the invention is to establish a method for enhancing the treatment of the silicon surface being etched, by using the differences in the energies of activation of the reactive gases to arrive at optimal conditions for both etching and passivation, and alternating those conditions at a high rate to produce a high aspect ratio, and high selectivity etch process.
  • the object of the present invention is accomplished by providing a method of anisotropic plasma etching of substrates (typically silicon) comprising the following steps:
  • step (c) concurrent with step (c), applying high polarizing voltage (50-500 eV) to the substrate via its electromagnet power source to produce a highly anisotropic etch;
  • step (e) concurrent with step (e), applying low polarizing voltage (0-25 eV) to the substrate to form a conformal polymer coating on the exposed side walls of the surfaces being etched;
  • the method used in this invention enables the substrate to be etched without using helium gas as a cooling medium. This is because lower power is used to excite the etching gas resulting in less heat being generated during the process.
  • a further advantage of this invention is that a constant flow of mixed gas is injected into the process chamber during processing, resulting in a process that is more stable and repeatable.
  • FIG. 1 is a schematical view showing the etching device for use in the present invention.
  • FIGS. 2 ( a ) to 2 ( c ) are views showing the process steps of the present invention.
  • the device includes an etching chamber 10 .
  • a substrate holder 12 for holding substrate 14 as well as an inductive coupler 16 provided near the top of the chamber 10 .
  • the substrate holder 12 is an electrode which is electrically connected to generator 18 , including a power supply 19 and a matching network 21 , for polarizing the substrate 14 .
  • generator 18 Located at the top of the chamber is an inlet line 20 for introducing process gases into the chamber.
  • the process gases are stored in gas tanks 22 , 24 and 26 .
  • the flow rate of the process gases into the chamber 10 is controlled by a control valves 28 .
  • the plasma stimulation is provided by inductive coupler 16 powered by an RF power source 30 and an associated matching network 32 .
  • Pressure within the chamber 10 is controlled by mechanical pump 34 , turbo-molecular pump 36 and throttle valve 38 , in the conventional manner. It is of course understood that the invention is not limited to this particular device.
  • the substrate 14 including a silicon substrate 40 and an etching mask 40 that exposes the regions of the silicon substrate 40 that are intended to be anisotropically etched, is placed on the substrate holder/electrode 12 and subjected to the first etching step.
  • a mixture of gases containing etchant and passivating gases e.g., SF 6 , C 4 F 8 , and CHF 3
  • a certain flow rate preferably in the range of 100 to 400 sccm and pressure in the range of 0.1 to 10 Pa
  • the plasma is stimulated by applying a relatively low RF power, preferably in the range of 100 to 800 W, from the power source 30 .
  • a polarization potential is provided by the substrate generator 18 to produce an electrical field of a relatively high value in the range of 50 to 500 eV, and preferably 80-300 eV.
  • the low RF power applied for plasma stimulation provides the directional etch with an extremely high rate. Specifically, the plasma is “cold” due to the low energy applied so that the directionality of the ions can be controlled.
  • the high potential of the substrate 14 provides strong acceleration of the ions toward the etched surface. Both factors provide excellent directionality of the ions, resulting in a high anisotropic etch.
  • the etched portion 44 of the silicon substrate 40 is shown in FIG. 2 ( a ).
  • the power source 30 switches to a relatively high power, preferably in the range of 1000 to 3000 W, to create high energy excitation of the plasma and the polarization potential developed by the substrate generator is reduced to a relatively low, or even zero, value (i.e. 0-25 eV).
  • High energy excitation of the plasma creates a condition that results in the formation of a polymer layer 46 .
  • isotropic movement of species causes the thickness of the polymer layer 46 on the bottom of the trench to be the same as the thickness on the sidewalls, as shown in FIG. 2 ( b ).
  • the low polarization on the substrate 14 prevents any etching.
  • the protective polymer layer 46 of a predetermined thickness is formed on the trench walls, as shown in FIG. 2 ( b ). This protective polymer layer 46 prevents erosion of the trench walls that were formed in the previous etching steps during the subsequent etching step, performed in the manner discussed above.
  • the previously etched sidewalls remain protected by the polymer layer 46 , while the polymer layer on the bottom of the trench is rapidly stripped by the anisotropic bombardment of the ions that are accelerated by the high polarizing potential, allowing the silicon at the base of the trench to be further etched, as identified by reference numeral 48 in FIG. 2 ( c ).
  • the etching and passivating steps are alternately repeated until the trench reaches the required depth.
  • the time for the species to arrive at the bottom of the etched trench varies drastically for trenches with different sized openings. This increases the variation in the depths achieved for trenches with different aspect ratios (Aspect Ratio Dependent Etch).
  • the gas composition will be uniform for trenches with different size openings. This also improves the uniformity (microloading effect).
  • the method of the present invention provides very high selectivity to the mask material, due to the combination of low power used during the etch and low polarization voltage used during deposition.
  • Additional silicon etching gases include CF 4 , NF 3 , NF3HF, HBr, CCL 4 , CF 2 Cl 2 , CFCl 3 , Br 2 , Cl 2 , I 2 , HCl, CIF 3 and BCl 3 .
  • additional passivation gases include CH 4 , CH 2 F 2 , H 2 , C 2 H 4 , C 3 H 8 , CH 3 Br, C 2 F 6 , C 2 F 4 , and C 3 F 6 .
  • the etch or passivation effect may be achieved by alternating the pressure in the chamber.
  • the polymer formation during passivation is effected by the pressure.
  • an increase in pressure during etching increases the etching rate, while a decrease in pressure decreases the etching rate.

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  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)
  • Weting (AREA)
US09/295,100 1999-04-21 1999-04-21 Method of anisotropic etching of substrates Expired - Lifetime US6383938B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US09/295,100 US6383938B2 (en) 1999-04-21 1999-04-21 Method of anisotropic etching of substrates
AT00400462T ATE341099T1 (de) 1999-04-21 2000-02-21 Verfahren zur anisotropen ätzung von substraten
EP00400462A EP1047122B1 (de) 1999-04-21 2000-02-21 Verfahren zur anisotropen Ätzung von Substraten
DE60030905T DE60030905T2 (de) 1999-04-21 2000-02-21 Verfahren zur anisotropen Ätzung von Substraten
JP2000055248A JP4601113B2 (ja) 1999-04-21 2000-03-01 基板の異方性エッチング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/295,100 US6383938B2 (en) 1999-04-21 1999-04-21 Method of anisotropic etching of substrates

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US20010044213A1 US20010044213A1 (en) 2001-11-22
US6383938B2 true US6383938B2 (en) 2002-05-07

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US (1) US6383938B2 (de)
EP (1) EP1047122B1 (de)
JP (1) JP4601113B2 (de)
AT (1) ATE341099T1 (de)
DE (1) DE60030905T2 (de)

Cited By (10)

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Publication number Priority date Publication date Assignee Title
US20050029226A1 (en) * 2003-08-07 2005-02-10 Advanced Power Technology, Inc. Plasma etching using dibromomethane addition
US6921723B1 (en) * 2002-04-23 2005-07-26 Applied Materials, Inc. Etching method having high silicon-to-photoresist selectivity
US20060168794A1 (en) * 2005-01-28 2006-08-03 Hitachi Global Storage Technologies Method to control mask profile for read sensor definition
US20070166844A1 (en) * 2004-07-02 2007-07-19 Yasuhiro Morikawa Ethcing method and system
US20100270598A1 (en) * 2009-04-23 2010-10-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming highly strained source/drain trenches
CN102044410A (zh) * 2009-07-27 2011-05-04 朗姆研究公司 减少微负载的等离子体蚀刻方法
US20120034785A1 (en) * 2010-08-05 2012-02-09 Hisataka Hayashi Semiconductor device manufacturing method
US9443852B2 (en) 2014-02-19 2016-09-13 Samsung Electronics Co., Ltd. Integrated circuit devices with source/drain regions including multiple segments
US9607847B1 (en) * 2015-12-18 2017-03-28 Texas Instruments Incorporated Enhanced lateral cavity etch
US9941121B1 (en) 2017-01-24 2018-04-10 International Business Machines Corporation Selective dry etch for directed self assembly of block copolymers

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US20050158666A1 (en) * 1999-10-15 2005-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple etch method for etching material etchable with oxygen containing plasma
DE10247913A1 (de) * 2002-10-14 2004-04-22 Robert Bosch Gmbh Plasmaanlage und Verfahren zum anisotropen Einätzen von Strukturen in ein Substrat
US20040077178A1 (en) * 2002-10-17 2004-04-22 Applied Materials, Inc. Method for laterally etching a semiconductor structure
JP4065213B2 (ja) * 2003-03-25 2008-03-19 住友精密工業株式会社 シリコン基板のエッチング方法及びエッチング装置
JP4161857B2 (ja) * 2003-09-10 2008-10-08 株式会社デンソー 半導体装置の製造方法
DE10345402B4 (de) * 2003-09-30 2005-10-13 Infineon Technologies Ag Verfahren zur Bearbeitung einer Halbleiterstruktur mit einer Vertiefung
US7183215B2 (en) * 2004-07-21 2007-02-27 Hewlett-Packard Development Company, L.P. Etching with electrostatically attracted ions
FR2880469B1 (fr) * 2005-01-03 2007-04-27 Cit Alcatel Dispositif de fabrication d'un masque par gravure par plasma d'un substrat semiconducteur
DE102005031602A1 (de) * 2005-07-06 2007-01-11 Robert Bosch Gmbh Reaktor zur Durchführung eines Ätzverfahrens für einen Stapel von maskierten Wafern und Ätzverfahren
WO2007031778A1 (en) * 2005-09-16 2007-03-22 Aviza Technology Limited A method of etching a feature in a silicone substrate
JP5845754B2 (ja) * 2010-09-15 2016-01-20 東京エレクトロン株式会社 プラズマエッチング処理方法
US9318341B2 (en) * 2010-12-20 2016-04-19 Applied Materials, Inc. Methods for etching a substrate
KR101251072B1 (ko) * 2011-07-12 2013-04-12 에이피티씨 주식회사 반도체소자의 식각방법
CN103159163B (zh) * 2011-12-19 2016-06-08 北京北方微电子基地设备工艺研究中心有限责任公司 基片刻蚀方法及基片处理设备
CN104134611B (zh) * 2013-05-03 2017-09-29 无锡华润上华半导体有限公司 硅释放工艺
JP2015032597A (ja) * 2013-07-31 2015-02-16 日本ゼオン株式会社 プラズマエッチング方法
US9978606B2 (en) * 2015-10-02 2018-05-22 Applied Materials, Inc. Methods for atomic level resolution and plasma processing control
CN106653594B (zh) * 2015-10-30 2019-05-28 中微半导体设备(上海)股份有限公司 一种在高宽比硅刻蚀中用于提高侧壁刻蚀效果的方法
US9691625B2 (en) * 2015-11-04 2017-06-27 Lam Research Corporation Methods and systems for plasma etching using bi-modal process gas composition responsive to plasma power level
KR102489215B1 (ko) * 2016-09-06 2023-01-16 도쿄엘렉트론가부시키가이샤 유사 원자층 에칭 방법
US20210040596A1 (en) * 2018-05-17 2021-02-11 Evatec Ag Method of treating a substrate and vacuum deposition apparatus
US11393703B2 (en) 2018-06-18 2022-07-19 Applied Materials, Inc. Apparatus and method for controlling a flow process material to a deposition chamber
JP7692696B2 (ja) * 2020-10-19 2025-06-16 東京エレクトロン株式会社 基板処理方法および基板処理装置
KR20230085168A (ko) * 2020-10-19 2023-06-13 도쿄엘렉트론가부시키가이샤 기판 처리 방법 및 기판 처리 장치
JP7621145B2 (ja) * 2021-03-15 2025-01-24 東京エレクトロン株式会社 基板処理方法および基板処理装置
CN117080062B (zh) * 2023-10-13 2024-01-26 无锡邑文微电子科技股份有限公司 碗状刻蚀的方法
EP4557348A1 (de) * 2023-11-16 2025-05-21 AlixLabs AB Zyklische verarbeitung einer siliziumnanostruktur
WO2026064073A1 (en) * 2024-09-17 2026-03-26 Lam Research Corporation Selective etch with passivation tuning

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6921723B1 (en) * 2002-04-23 2005-07-26 Applied Materials, Inc. Etching method having high silicon-to-photoresist selectivity
US20050029226A1 (en) * 2003-08-07 2005-02-10 Advanced Power Technology, Inc. Plasma etching using dibromomethane addition
WO2005017961A3 (en) * 2003-08-07 2006-05-18 Advanced Power Technology Plasma etching using dibromomethane addition
US20070166844A1 (en) * 2004-07-02 2007-07-19 Yasuhiro Morikawa Ethcing method and system
US7728252B2 (en) 2004-07-02 2010-06-01 Ulvac, Inc. Etching method and system
US20060168794A1 (en) * 2005-01-28 2006-08-03 Hitachi Global Storage Technologies Method to control mask profile for read sensor definition
US8071481B2 (en) * 2009-04-23 2011-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming highly strained source/drain trenches
US20100270598A1 (en) * 2009-04-23 2010-10-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming highly strained source/drain trenches
US10868166B2 (en) 2009-04-23 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Highly strained source/drain trenches in semiconductor devices
CN102044410A (zh) * 2009-07-27 2011-05-04 朗姆研究公司 减少微负载的等离子体蚀刻方法
CN102044410B (zh) * 2009-07-27 2015-11-25 朗姆研究公司 减少微负载的等离子体蚀刻方法
US20120034785A1 (en) * 2010-08-05 2012-02-09 Hisataka Hayashi Semiconductor device manufacturing method
US8536061B2 (en) * 2010-08-05 2013-09-17 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US9443852B2 (en) 2014-02-19 2016-09-13 Samsung Electronics Co., Ltd. Integrated circuit devices with source/drain regions including multiple segments
US9607847B1 (en) * 2015-12-18 2017-03-28 Texas Instruments Incorporated Enhanced lateral cavity etch
US20170178916A1 (en) * 2015-12-18 2017-06-22 Texas Instruments Incorporated Enhanced lateral cavity etch
US9941121B1 (en) 2017-01-24 2018-04-10 International Business Machines Corporation Selective dry etch for directed self assembly of block copolymers

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EP1047122A2 (de) 2000-10-25
ATE341099T1 (de) 2006-10-15
DE60030905D1 (de) 2006-11-09
EP1047122B1 (de) 2006-09-27
JP2000323454A (ja) 2000-11-24
US20010044213A1 (en) 2001-11-22
DE60030905T2 (de) 2007-09-20
EP1047122A3 (de) 2001-12-05
JP4601113B2 (ja) 2010-12-22

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