WO1987007763A1 - Procede de fabrication de dispositifs par deposition en phase gazeuse par procede chimique, et dispositifs ainsi realises - Google Patents

Procede de fabrication de dispositifs par deposition en phase gazeuse par procede chimique, et dispositifs ainsi realises Download PDF

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Publication number
WO1987007763A1
WO1987007763A1 PCT/US1987/001230 US8701230W WO8707763A1 WO 1987007763 A1 WO1987007763 A1 WO 1987007763A1 US 8701230 W US8701230 W US 8701230W WO 8707763 A1 WO8707763 A1 WO 8707763A1
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Prior art keywords
metal
drain
source
silicon
drains
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Patrick Kent Gallagher
Martin Laurence Green
Roland Albert Levy
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AT&T Corp
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American Telephone and Telegraph Co Inc
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Priority to KR1019880700174A priority Critical patent/KR920010125B1/ko
Priority to JP62503471A priority patent/JPH0680682B2/ja
Publication of WO1987007763A1 publication Critical patent/WO1987007763A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour

Definitions

  • the invention pertains generally to a method for fabricating devices, e.g., semiconductor devices, as well as the resulting devices. % Art Rackgronnd
  • metal-containing materials i.e., pure metals, molecular-type materials in which the molecules include one or more metal atoms, and/or mixtures which include one or more of the above, onto a processed or unprocessed substrate plays a significant role in the fabrication of a variety of devices.
  • Such devices include, for example, discrete semiconductor devices, integrated circuit devices, and magnetic bubble devices.
  • the deposition of, for example, a pure metal onto selected regions of a processed or unprocessed semiconductor substrate is accomplished by forming a patterned deposition mask, e.g., a patterned photoresist layer, on the substrate surface, and then e-beam evaporating or rf-sputtering the metal onto the mask-bearing substrate surface. Subsequent removal of the mask leaves the metal covering only the selected substrate regions.
  • a patterned deposition mask e.g., a patterned photoresist layer
  • the metal is deposited directly onto the substrate surface, and a patterned etch mask, e.g., a patterned photoresist layer, formed on the metal. Then, the metal is etched through the etch mask, and the etch mask is removed, again leaving metal only in the selected regions.
  • MOS metal-oxide- semiconductor
  • MOSFET metal-oxide-semiconductor field effect transistors
  • Each MOSFET also includes a relatively thin gate oxide (GOX) formed on the surface of the active layer, a conducting gate of, for example, doped polycrystalline silicon (polysilicon), formed on the surface of the GOX, and two relatively heavily doped portions of the active layer, on opposite sides of the gate, which constitute the source and drain of the MOSFET.
  • GOX gate oxide
  • polysilicon doped polycrystalline silicon
  • a relatively thick (compared to the GOX) field oxide (FOX) serves to separate and electrically insulate the MOSFETs from one another.
  • the MOS ICs also include metal, e.g., aluminum or aluminum-copper alloy, contacts to, and metal runners extending from, the sources, drains, and gates of the MOSFETs, through which electrical communication is achieved with the MOSFETs. These metal contacts and runners are formed using the deposition and patterning techniques, described above.
  • an electrically insulating glass e.g., a glass which includes SiO 2 -P 2 O 5 or SiO 2 -P 2 O 5 -B 2 O 3
  • an electrically insulating glass is first deposited onto the MOSFETs and FOX of an IC using conventional chemical vapor deposition (CVD) techniques, to serve as an interlevei dielectric (an electrically insulating layer) between the gate metallization and the source/drain metallization.
  • CVD chemical vapor deposition
  • a metallic conductor such as aluminum is deposited, e.g., rf-sputtered or e-beam evaporated, onto the interlevei dielectric, as well as into the via holes, to form the electrical contacts to the sources, drains and gates.
  • the deposited (onto the interlevei dielectric) aluminum is then etched through a patterned etch mask, e.g., a patterned photoresist layer, to form the interconnecting runners which- terminate in contact pads.
  • metal-containing materials onto device substrates often involves undesirable interactions between the deposited material and the substrates.
  • semiconductor materials such as silicon
  • aluminum from the overlying metal contacts diffuses into the underlying silicon to produce what are termed aluminum spikes.
  • aluminum constitutes a p-type dopant for silicon.
  • an aluminum spike were to extend through an n-type source or drain (into a p-type substrate), the p-n junction at the source-substrate or drain-substrate interface would be eliminated.
  • aluminum spikes typically extend less than about one micrometer ( ⁇ m) into silicon, their presence is generally not significant in devices where the source and drain p-n junctions have depths greater than or equal to about 1 ⁇ m. Conversely, these spikes pose a serious problem in devices where the p-n junction depths are less than about 1 ⁇ m, the very type of devices which, it is expected, will shortly be coming into commercial use.
  • Such precipitation results in the metal contacts to the n sources and drains (typically doped to a level greater than or equal to about 10 cm " ) exhibiting undesirably high contact resistivities, i.e., contact resistivities higher than about 10 -5 ohm-cm 2 , and thus exhibiting undesirably high contact resistances; (By contrast, the ' contact resistivities to the p sources and drains are only higher than or equal to about 10 -6 ohm-cm 2. )
  • tungsten can be selectively deposited onto sources and drains, without the use of a patterned deposition mask and without the need for subsequent etching, using either of two low pressure CVD (LPCVD) techniques.
  • LPCVD low pressure CVD
  • Fg tungsten hexafluoride
  • the WF fi preferentially reacts with the Si of the exposed source and drain regions to form W (a solid) on these regions and SiF . (a gas, exhausted from the reaction chamber) via the overall chemical reaction 2WF Q +3Si ⁇ 2W+ZSiF 4 .
  • both WF ⁇ and H 2 are flowed across the processed silicon substrate (with the total pressure of all the gases within the reaction chamber conventionally maintained at about 1 torr). Initially, the WF ⁇ reacts with the Si of the exposed sources and drains to form (as discussed above, what is reported to be) a relatively thin layer of W.
  • the W covering the exposed source and drain regions, but not the SiO 2 of the interlevei dielectric serves to catalyze a chemical reaction between the WF ⁇ and EL which yields additional W (formed on the sources and drains) and HF (a gas, exhausted from the reaction chamber) via the overall chemical reaction
  • the invention involves a device fabrication method which includes the step of reacting at least two entities for the purpose of forming a metal- containing material on a region, or regions, or all of a processed or unprocessed substrate.
  • this desired reaction is accompanied (or even preceded) by a second reaction between one (or more) of the reactive entities and substrate material, e.g., semiconductor material (to be found in an unprocessed or processed substrate), metal (to be found on a processed substrate), or Si0 2 (to be found on a processed substrate).
  • substrate material e.g., semiconductor material (to be found in an unprocessed or processed substrate), metal (to be found on a processed substrate), or Si0 2 (to be found on a processed substrate).
  • substrate material e.g., semiconductor material (to be found in an unprocessed or processed substrate), metal (to be found on a processed substrate), or Si0 2 (to be found on a processed substrate).
  • substrate material e.g., semiconductor material (to be found in an un
  • the contact resistivities of aluminum contacts to (W-covered) p and n sources and drains having depths less than about 1 ⁇ m are far higher than those previously reported to (W- covered) p and n sources and drains having depths greater than, or equal to, about 1 ⁇ m.
  • the contact resistivities to (W-covered) p sources and drains having depths less than about 1 ⁇ m have been found to be higher than about 5 x 10 -5 ohm-cm 2.
  • the contact resistivities to (W- covered) n sources and drains having depths less than about 1 ⁇ m have been found to be higher than about 10 -5 ohm-cm 2.
  • the inventive device fabrication method is distinguished from previous such methods in that it involves a variety of techniques for preventing, or significantly reducing the degree of, the adverse consequences associated with the second (undesirable) reaction. That is, techniques have been developed for reducing the rate of (the undesirable) reaction between the substrate material and one (or more) of the at least two reactive entities, without inducing a substantial reduction in the rate of the (desired) reaction between the at least two reactive entities.
  • the reaction rate (associated with the undesirable reaction) between WF ⁇ and Si is reduced, without significantly reducing the reaction rate between WF ⁇ and H 2 by, for example, increasing the concentration of one of the products of the undesirable reaction, i.e., increasing the concentration of SiF . (above what normally occurs).
  • the erosion of both n and p sources and drains is substantially reduced, the reduction being particularly significant in devices having n sources and drains with depths less than about 1 ⁇ m.
  • the contact resistivities to both the n and p sources and drains are also substantially reduced, to levels less than or equal to about 10 -6 ohm-cm 2.
  • FIGS. 1-7 depict the steps involved in one embodiment of the inventive device fabrication method.
  • FIGS. 8-10 depict device contact resistances achieved using previous fabrication methods and the inventive device fabrication method. Detailed Description
  • the invention involves a method for fabricating devices, e.g., discrete semiconductor devices, integrated circuit devices, and magnetic bubble devices, the method including the step of forming a metal-containing material on a region, or regions, or all of a processed or unprocessed substrate.
  • the invention also involves the devices resulting from the inventive method.
  • a metal-containing material is achieved, in accordance with the invention, by reacting at least two reactive entities (other than substrate material), at least one of the entities including metal of the type contained in the metal-containing material.
  • the reaction between the at least two reactive entities is, in many instances, accompanied by a second reaction (or series of reactions) between one (or more) of the reactive entities and substrate material.
  • this second reaction often produces previously unrecognized, and highly undesirable, results.
  • one (or more) of a variety of techniques is used to reduce the reaction rate associated with the second, undesirable reaction.
  • these techniques are chosen so that the reaction rate between the two reactive entities is not substantially reduced. (For purposes of the invention, such a substantial reduction is avoided provided the rate of formation of the metal-containing material is greater than about 0.1 nm per minute.)
  • the WF ⁇ when reacting WF ⁇ with EL to form W on the silicon surfaces of MOSFET sources and drains, the WF ⁇ necessarily also reacts with the silicon to erode the sources and drains, the degree of erosion of the n sources and drains being far greater than that of the p sources and drains.
  • n sources and drains having depths less than about 1 ⁇ m are significantly eroded, and often almost entirely eroded away.
  • the depth of a source or drain is defined to be the length of a perpendicular extending from a least- squares-fit planar approximation to the original substrate surface to the lowest point where the dopant concentration in the source or drain is equal to the dopant concentration in the surrounding substrate. This point is determined, for example, by SIMS analysis, or by conventional junction staining techniques. Regarding these staining techniques see, e.g., Quick Reference Manual fo ⁇ Silicon Integrated Circuit Technology, edited by W. E. Beadle et al (John Wiley and Sons, New York, 1985, section 5-9.)
  • WF ⁇ and H 2 are flowed into the reaction chamber at respective flow rates of, for example, 10 seem (standard cubic centimeters per minute) and
  • SiF is flowed into the reaction chamber at a flow rate ranging from about 1 seem to about 100 seem. Flow rates of SiF 4. less than about
  • reaction temperatures outside the conventional temperature range i.e., temperatures less than about 250 degrees C and temperatures greater than about 600 degrees C, has the same desirable effect, although temperatures greater than about 600 degrees C produce a reduction in the selectivity of W- formation.
  • the techniques, described above, are not only useful in forming W, but are also useful in forming a wide variety of metal-containing materials.
  • metals such as molybdenum, tantalum, titanium and rhenium, and their corresponding suicides
  • metals such as molybdenum, tantalum, titanium and rhenium, and their corresponding suicides
  • metals are readily formed by reacting the fluorides or chlorides of these metals, e.g., MoF ⁇ , TaC , TiC , and ReF ⁇ , with a reducing agent such as EL (to form the metals) or SiH. (to form the suicides).
  • EL to form the metals
  • SiH to form the suicides
  • the metal fluorides or chlorides tend to react with silicon, producing the undesirable results, discussed above.
  • the reaction rates associated with these undesirable reactions are readily reduced, using the techniques described above.
  • the inventive device fabrication method to the fabrication of an MOS IC which includes an n-channel MOSFET, e.g., an n- channel MOS IC or a CMOS IC, is described below.
  • the n-channel MOSFET includes n sources and drains having depths less than about 1 ⁇ m.
  • this MOSFET includes diffusion barriers, e.g., tungsten diffusion barriers, at the sources and drains, to prevent or reduce interdiffusion of aluminum and silicon, and thus prevent aluminum spikes from extending through the sources and drains.
  • MOS IC which includes an n-channel MOSFET is fabricated by forming relatively thin GOXs 30 and a relatively thick FOX 40 on the surface of a layer of doped semiconductor material 20.
  • the layer 20 constitutes the surface active layer of a substrate 10 of semiconductor material. If the MOS IC includes both n-channel and p-channel MOSFETs, then the substrate 10 will necessarily include both p-type and n-type bulk regions. In what follows, it is assumed the n-channel MOSFET is fabricated in a p-type bulk region having a doping level
  • the relatively thick FOX 40 separates the GOX-covered GASAD (gate- and-source-and-drain) areas 50, on the surface of the layer 20, where MOSFETs are to be formed. If, for example, the active layer 20 is of silicon, then the GOXs 30 and the FOX 40 will typically be, respectively, relatively thin and thick layers of SiQ 2 .
  • the FOX 40 is formed, for example, by thermally oxidizing the surface of the layer 20. After opening windows in the FOX (by conventional techniques) to expose the GASAD areas 50 on the surface of the layer 20, the GOXs 30 are formed, for example, by again thermally oxidizing the surface of the layer 20.
  • the thickness of the SiO 2 GOXs 30 ranges from about 15 nm to about 100 nm and is preferably about 20 nm. Thicknesses of the GOXs 30 less than about 15 nm are undesirable because such thin layers are likely to undergo dielectric breakdown. On the other hand, thicknesses greater than about 100 nm are undesirable because device operation requires the application of undesirably high voltages.
  • the thickness of the SiO 2 FOX 40 of the MOS IC ranges from about 200 nm to about 800 nm and is preferably about 400 nm. A thickness less than about 200 nm is undesirable because voltages applied to runners may invert underlying semiconductor material. On the other hand, a thickness greater than about 800 nm is undesirable because so thick a layer makes it difficult to subsequently achieve conformal deposition of metals, such as aluminum.
  • a layer of gate material e.g., a layer of polysilicon, is deposited onto the GOXs as well as onto the FOX, and then patterned (by conventional techniques) to form the gates 60.
  • the thickness of the deposited gate material ranges from about 200 nm to about 800 nm and is preferably about 600 nm. Thicknesses less than about 200 nm are undesirable because such thin layers have undesirably high sheet resistance and may be excessively eroded during etching of the via holes through the interlevei dielectric. Thicknesses greater than about 800 nm are undesirable because it is difficult to achieve essentially vertical, gate sidewalls when etching such thick layers.
  • dopants which are subsequently diffused into the active layer 20 to form the sources and drains of the MOSFETs
  • the useful dopants include, for example, phosphorus, arsenic, and antimony.
  • the incident energies of these dopants ranges from about 10 keV to about 300 keV, and is preferably about 100 keV. Energys less than about 10 keV are undesirable because the resulting junctions are undesirably shallow. Energys greater than about 300 keV are undesirable because the resulting junctions are undesirably deep, i.e., extend to a depth greater than 1 ⁇ m after diffusion.
  • the substrate 10 will also include an n-type bulk region (in which the p-channel MOSFETs are formed) having a typical doping level of about 10 cm " .
  • the useful p-type dopants to be implanted into the active layer of the n-type bulk region, e.g., n-type silicon, for subsequently forming the sources and drains of the p-channel MOSFETs include boron, aluminum, and gallium. The incident energies of these dopants is generally the same as that given above.
  • the interlevei dielectric 70 is now deposited onto the FOX 40, the gates 60, as' well as onto the implanted portions of the GASAD regions 50.
  • the interlevei dielectric 70 includes, for example, SiO 2 -P 2 O 5 or SiO 2 -P 2 Oc-B 2 Og, materials which are readily deposited using conventional CVD techniques.
  • the thickness of the interlevei dielectric 70 ranges from about 1/2 ⁇ m to about 2 ⁇ m, and is preferably about 1 ⁇ m. Thicknesses less than about 1/2 ⁇ m are undesirable because such thin layers are relatively poor insulators. Thicknesses greater than about 2 ⁇ m are undesirable because such thick layers result in relatively poor step coverage during subsequent metallization.
  • the upper surface of the deposited interlevei dielectric 70 is typically nonplanar (which is generally undesirable during subsequent processing).
  • the substrate is heated to temperatures ranging from about 850 degrees C to about 1100 degrees C, over corresponding time periods ranging from about 1 hour to about 2 hours. Temperatures less than about 850 degrees C, and heating times less than about 1 hour, are undesirable because they produce an undesirably small amount of glass flow. Further, temperatures greater than about 1100 degrees C, and heating times greater than about 2 hours, are undesirable because they produce undesirably deep junctions.
  • the interlevei dielectric is patterned (using conventional techniques) to open via holes 100, 110, and 120 to, respectively, the sources, drains, and gates. If the electrical, contacts (to be subsequently formed) * to the sources, drains and gates are to- include aluminum, and the substrate 10 is of silicon, then a barrier (130, 140) to the interdiffusion of aluminum and silicon is formed over each source and drain. Simultaneously, a layer 150 is formed over the gate 60.
  • the diffusion barrier includes, for example, a region of tungsten. Alternatively, this barrier includes a region of titanium, tantalum, molybdenum or rhenium.
  • the thickness of the diffusion barrier ranges from about 30 nm to about 150 nm and is preferably about 100 nm. Thicknesses less than about 30 nm are undesirable because such thin regions are relatively poor diffusion barriers. Thicknesses greater than 150 nm are undesirable because, for example, they lead to loss of selectivity in tungsten formation. If the diffusion barriers 130 and 140 are of tungsten, then useful thicknesses of tungsten are readily selectively formed on the sources and drains by reacting WF ⁇ and EL. Moreover, and to reduce the excessive etching of the n sources and drains, excess SiF , is also introduced. The flow rate of the WF ⁇ ranges from about 1 seem to about 30 seem, and is preferably about 10 seem.
  • a flow rate less than about 4 seem is undesirable because it results in an undesirably low rate of tungsten formation.
  • a flow rate greater than about 30 seem is undesirable because it leads to excessive corrosion of the apparatus used in forming the tungsten.
  • the flow rate of the H 2 ranges from about 100 seem to about 5000 seem, and is preferably about 2000 seem. Flow rates less than about 100 seem are undesirable because they lead to excessive silicon erosion. Flow rates greater than about 5000 seem are undesirable because they lead to undesirably high total pressures.
  • the flow rate of the SiF . ranges from 1 seem to about 100 seem, and is preferably about 20 seem. Flow rates less than about 1 seem and greater than about 100 seem are undesirable for the reasons given above.
  • the total pressure of the gases involved in the selective formation procedure ranges from about 13 Pa (100 millitorr) to about 267 Pa (2 torr), and is preferably about 133 Pa (1 torr).
  • the reaction temperature ranges from about 250 degrees C to about 600 degrees C, and is preferably about 300 degrees C or about 550 degrees C.
  • Total pressures less than about 13 Pa (100 millitorr), and reaction temperatures less than about 250 degrees C, are undesirable because they result in relatively low tungsten formation rates.
  • Total pressures greater than about 267 Pa (2 torr) are undesirable because they can lead to gas-phase nucleation of tungsten, rather than nucleation on the surfaces of the sources and drains.
  • Reaction temperatures greater than about 600 degrees C are undesirable because they result in a loss of selectivity in tungsten formation.
  • a layer of metal 160 e.g., an aluminum layer, is deposited onto the interlevei dielectric 70, as well as into the via holes leading to the sources, drains and gates.
  • the thickness of the layer 160 ranges from about 1/2 ⁇ m to about 2 ⁇ m. Thicknesses less than about 1/2 ⁇ m are undesirable because they lead to undesirably high sheet resistance. Thicknesses greater than about 2 ⁇ m are undesirable because it is difficult to achieve essentially vertical sidewalls during the patterning of such thick layers.
  • the metal layer 160 is patterned (not shown), e.g., selectively reactive ion etched, to form interconnecting metal runners which terminate in metal contact pads.
  • the resulting substrate is then annealed at temperatures of, for example,
  • the MOS IC is finally completed by a series of conventional steps which typically includes the deposition of a silicon nitride layer, by the conventional technique of plasma-enhanced CVD, onto the IC to form a barrier against moisture and mechanical damage.
  • the MOS IC is distinguishable from previous such ICs in that the formation of the diffusion barriers results in n sources and drains which are substantially free of erosion.
  • a source or drain is substantially free of erosion, for purposes of the invention, provided the length of a perpendicular extending from a least-squares- fit planar approximation to the original substrate surface to the lowest point of the interface between the diffusion barrier and the source or drain is less than or equal to about 30 nm.
  • the metal contacts to all the sources and drains of the IC, including the source and drain of the n-channel MOSFET exhibit contact resistivities which are less than about 10 -6 ohm-cm 2 , and typically even less than
  • the contact resistivity to a source or drain is the multiple of the contact resistance, R , to the source or drain and the area, A, of the upper surface of the source or drain.
  • the former is readily determined by first measuring the current-voltage (I-V) curve across a region of the device substrate containing the source or drain.
  • the area, A, of the upper surface, and the depth, d_, of the source or drain are then measured using conventional techniques such as scanning electron microscopy, transmission electron microscopy, or secondary ion mass spectroscopy. Based upon the measured values of A and d_, the ideal I-V curve for the source or drain is then calculated as taught, for example, in S. M. Sze,
  • R is readily measured by applying an increasing,- forward-biasing voltage across the source or drain, and measuring the corresponding values of dV/dl, the derivative of the applied voltage with respect to the resulting source/drain current.
  • the contact resistance is equal to the value of dV/dl at saturation, i.e., when dV/dl stops changing with increasing forward-bias.
  • the above MOS IC is preferably fabricated to include a region of metal suicide, i.e., cobalt suicide, titanium suicide, platinum suicide, tantalum suicide, or molybdenum suicide, on the sources and drains, prior to forming the diffusion barriers, as described above.
  • the metal suicide regions are advantageous because they result in thermally stable contact resistivities to the sources and drains of the MOS IC, including the source and drain of the n-channel MOSFET, which are even lower than those described above, i.e., lower than about 10 -6 ohm-cm 2 , and even lower than about 10 -7 ohm-cm 2.
  • Useful thicknesses of the metal suicide range from about
  • Thicknesses less than about 30 nm are undesirable because such thin layers are often incapable of preventing the overlying metal from penetrating- to the substrate, resulting in increased contact resistivities. Thicknesses greater than about 100 nm are undesirable because such thick layers require the consumption of an undesirably large amount of substrate material during suicide formation.
  • the metal suicide regions are formed by depositing, e.g., rf- sputtering, the corresponding pure metal into the via holes in the interlevei dielectric, and then sintering (thus reacting the metal with the silicon of the sources and drains) in an inert atmosphere of, for example, argon.
  • Useful thicknesses of deposited metal range from about 15 nm to about 50 nm Thicknesses less than about 15 nm and greater than about 50 nm are undesirable because they yield metal suicide thicknesses which are outside the range, given above.
  • Useful sintering temperatures, and corresponding sintering times range from about 300 degrees C and about 1 hour to about 1000 degrees C and about 1 hour.
  • Sintering temperatures less than about 300 degrees C, and sintering times less than about 1 hour, are undesirable because they yield incomplete reactions between the metal and the silicon.
  • Sintering temperatures greater than about 1000 degrees C, and sintering times greater than about 1 hour, are undesirable because they lead to undesirable reactions between the metal in the metal suicide and both silicon and silicon dioxide.
  • the use of the above-described sintering procedure to form the metal silicide regions does produce some erosion of the sources and drains. However, this erosion is typically relatively small compared to the erosion produced by the undesirable reaction between WF ⁇ and the silicon of the sources and drains.
  • the metal silicide regions are generally porous, and thus permit reactive entities, such as WF ⁇ , to react with, and thus erode, the silicon of the sources and drains.
  • the WF ⁇ tends to leach out, and react with, the silicon of the metal suicides.
  • the above-described inventive techniques are essential to preventing the erosion of the metal suicides, and to achieving substantially erosion-free sources and drains.
  • a diffusion barrier-and-metal silicide-covered source or drain is substantially free of erosion provided the length of a perpendicular extending from a particular imaginary plane to the lowest point of the interface between the metal silicide and the source or drain is less than or equal to about 30 nm.
  • the imaginary plane of interest is positioned below (within the substrate), and is parallel to, the least-squares-fit planar approximation to the original substrate surface.
  • the length of a perpendicular extending between the two planes is equal to the thickness of the corresponding, uniform layer of silicon consumed in forming the metal silicide. This thickness is readily inferable from the amount of metal in the metal silicide, which is readily determined using, for example, conventional Rutherford Back-Scattering techniques. If the source of silicon used in forming the metal silicide is not the source or drain, then the imaginary plane is just the least-squares-fit planar approximation to the original substrate surface.)
  • the first group here denoted Group I
  • the second group here denoted Group ⁇
  • the second group included 25 n-type wafers exhibiting resistivities of 10-20 ⁇ - cm.
  • a silicon dioxide layer having a thickness of about 10 nm, was thermally grown on each wafer.
  • relatively heavily doped p-type bulk regions were formed in the Group I wafers, and relatively heavily doped n-type bulk regions were formed in the Group II wafers, to simulate the p-tubs and n- tubs employed in CMOS devices. This was achieved by implanting boron ions
  • a layer of silicon nitride, having a thickness of about 120 nm was deposited onto each of the Group I and Group II wafers, using conventional LPCVD techniques. The silicon nitride layer on each wafer was then selectively reactive ion etched, in an atmosphere of CHF « and 0 consideration.
  • a field oxide (FOX) having a thickness of about 600 nm was thermally grown on the resulting, exposed surface regions of each wafer.
  • a gate oxide (GOX) having a thickness of about 25 nm, was thermally grown on each wafer, on the surface regions previously covered by the silicon nitride.
  • the Group I wafers received a 100 keV arsenic (an n-type dopant) implant, at various doses ranging from 8 x 10 14 cm -2 to 1 x 1016 cm -2 , the arsenic penetrating the GOX-covered regions but not the FOX-covered regions.
  • the Group II wafers received a 50 keV boron-difl ' uoride (a p-type dopant) implant, at various doses ranging from 8 x 10 cm “ to 1 x 10 cm " .
  • interlevei dielectric consisting of a 200 nm layer of undoped silicon dioxide, was deposited onto each wafer, using conventional LPCVD techniques. (The interlevei dielectrics were undoped to avoid contaminating p regions with phosphorus, an n-type dopant.) The interlevei dielectrics were then densified by heating the wafers to 900 degrees C for 30 minutes. In addition, the interlevei dielectrics were flowed, to planarize their upper surfaces, and the arsenic and phosphorus implants were activated and diffused into the wafers to form source/drain regions, by heating the wafers in an argon atmosphere at 950 degrees C for 60 minutes.
  • the interlevei dielectrics were selectively wet etched, using buffered HF, to form via holes to the source/drain regions. (Reactive ion etching was specifically avoided to preclude silicon erosion due to such etching.) Although the via holes were intended to be square, with 1.25 ⁇ m-long sides (as would have been achieved using anisotropic, reactive ion etching), the isotropic etching produced by the HF tended to widen the via holes to squares having sides as long as 2.2 ⁇ m. The processed wafers were separated into three categories (Categories I,
  • Categories I and II each included p-type (Group I) wafers having each of the various arsenic implant levels and n-type (Group II) wafers having each of the various boron-difluoride implant levels.
  • Category III included one p-type wafer and one n-type wafer.
  • a layer of tungsten was selectively deposited onto the source/drain regions of the Category I wafers, using a two-step process. That is, a tungsten film, having a thickness of about 15 nm, was initially selectively deposited (via the reaction given in Eq. (1)) onto the Category I wafers by flowing WF ⁇ across the wafers, for approximately 1 minute, at a temperature of 290 degrees C.
  • the total pressure within the deposition chamber was 400 Pa (3 torr), the partial pressure of the WF ⁇ being 0.67 Pa (5 millitorr) and the partial pressure of the argon constituting the remainder of the total pressure.
  • the total pressure within the deposition chamber was 186.7 Pa (1.4 torr), the partial pressure of the WF ⁇ being 1.3 Pa (10 millitorr) and the partial pressure of the EL accounting for the remainder of the total pressure.
  • the total pressure within the deposition chamber was 189.3 Pa (1.42 torr), the partial pressure of the WF ⁇ being 1.3 Pa (10 millitorr), the partial pressure of the SiF . being 6.7 Pa (20 millitorr), and the partial pressure of the IL, constituting the remainder of the total pressure.
  • the processing of the Category HI wafers differed from that of the Category II wafers only in that a layer of platinum silicide was formed on the source/drain regions prior to tungsten formation. That is, the Category HI wafers were initially cleaned with a HNCj/ELSO , solution. Then, a 20 nm- thick layer of platinum was sputter deposited onto the upper surfaces of the wafers, and the wafers were sintered at 650 degrees C for 15 minutes in a gaseous atmosphere which included 90 percent (by volume) argon and 10 percent oxygen. As a consequence, a layer of platinum silicide, having a thickness of about 40 nm, was selectively formed on the exposed, upper surfaces of the sources and drains. The remaining, unreacted platinum was removed using aqua regia. A 100:1 HF solution was used to clean these wafers prior to tungsten formation.
  • the contact resistance to the source and drain regions of all the wafers was measured, as a function of source/drain surface doping concentration, Nrv, using the conventional Kelvin technique (see, e.g., R. A. Levy, "In-Source Al- 0.5% Cu Metallization for CMOS Devices," Journal of the Electrochemical Society, Vol. 132, p.159, 1985).
  • the wafers were sintered at 330 degrees C for 45 minutes, and subsequently at 450 degrees C for 45 minutes, and the contact resistances were measured after each sintering procedure.
  • FIGS. 8-10 The measured contact resistances, as a function of N-r , are plotted in FIGS. 8-10. As is evident from FIGS. 8-9, which depict the results achieved with the Category I wafers, the contact resistances to p source/drain regions were higher than to n regions, at equivalent surface doping concentrations. In addition, the contact resistances to both n and p regions were thermally unstable, i.e., significantly increased after the sintering procedures.
  • FIG. 10 depicts the results achieved with the Category II and Category IH wafers.
  • the contact resistances to the p regions in the Category II wafers were equal to, or lower than, the contact resistances to the n regions, and both sets of contact resistances were thermally stable.
  • the Category III wafers exhibited significantly reduced, thermally stable contact resistances to both the n and p regions.
  • Scanning electron, and transmission electron, micrographs were made of samples taken from the Category I, II and HI wafers. These micrographs indicated that the source and drain regions in the Category II and HI wafers suffered much less vertical and lateral erosion than did the corresponding regions in the Category I wafers.

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

Procédé pour fabriquer un dispositif, par exemple un dispositif à semiconducteur, dans lequel on fait réagir au moins deux substances réactives afin de produire un matériau contenant du métal (par exemple 130 et 140; 150) dans une région ou des régions d'un substrat traité ou non traité. Le procédé tient compte du fait que l'une des substances réactives réagira souvent avec un matériau du substrat pour donner des résultats inattendus et très peu souhaitables, par exemple l'érosion presque totale d'éléments du dispositif qui ont déjà été réalisés. Par conséquent le procédé prévoit l'utilisation de l'une quelconque d'un ensemble de techniques afin de réduire la vitesse de réaction entre le matériau du substrat et la substance qui réagit avec celle-ci, tout en évitant une réduction substantielle de la vitesse de réaction entre les deux substances.
PCT/US1987/001230 1986-06-16 1987-05-27 Procede de fabrication de dispositifs par deposition en phase gazeuse par procede chimique, et dispositifs ainsi realises Ceased WO1987007763A1 (fr)

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KR1019880700174A KR920010125B1 (ko) 1986-06-16 1987-05-27 반도체 소자 제조 방법
JP62503471A JPH0680682B2 (ja) 1986-06-16 1987-05-27 デバイスの製造法

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WO (1) WO1987007763A1 (fr)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
US5814545A (en) * 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture

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EP0147913A2 (fr) * 1983-08-30 1985-07-10 Kabushiki Kaisha Toshiba Procédé pour la fabrication d'un dispositif semi-conducteur comportant une technique de croissance en vapeur sélective
EP0178200A1 (fr) * 1984-09-10 1986-04-16 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Procédé de régulation du dépôt chimique en phase vapeur
EP0194950A2 (fr) * 1985-03-15 1986-09-17 Fairchild Semiconductor Corporation Système d'interconnexion à haute température pour un circuit intégré

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EP0147913A2 (fr) * 1983-08-30 1985-07-10 Kabushiki Kaisha Toshiba Procédé pour la fabrication d'un dispositif semi-conducteur comportant une technique de croissance en vapeur sélective
EP0178200A1 (fr) * 1984-09-10 1986-04-16 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Procédé de régulation du dépôt chimique en phase vapeur
EP0194950A2 (fr) * 1985-03-15 1986-09-17 Fairchild Semiconductor Corporation Système d'interconnexion à haute température pour un circuit intégré

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Extended Abstracts, Volume 84, No. 1, 6-11 May 1984, (Pennington, New York, US),K.C. SARASWAT et al.: "Selective CVD of Tungsten for VLSI Technology", pages 114-115, Abstract 78 see the whole document *
IEEE Electron Device Letters, Volume EDL-5, No. 6, June 1984, IEEE, (New York, US), S. SWIRHUN et al.: "Contact Resistance of LPCVD W/AL and PtSi/W/AL Metallization" pages 209-211 see page 209, paragraph 2 *
Journal of the Electrochemical Society, Volume 132, No. 5, May 1985, (Manchester, New Hampshire, US), M.L. GREEN et al.: "Structure of Selective low Pressure Chemically Vapor-Deposited films of Tungsten", pages 1243-1250 see page 1244, paragraphs 3-8 *
Solid State Technology, Volume 27, No. 8, August 1984, (Port Washington, New York, US), J.Y. CHEN et al.: "Refractory Metals and Metal Silicides for VLSI Devides", pages 145-149 see pages 145, paragraph 6 - page 146, paragraph 4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814545A (en) * 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture

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KR920010125B1 (ko) 1992-11-16
CA1286798C (fr) 1991-07-23
JPH0680682B2 (ja) 1994-10-12
ES2006502A6 (es) 1989-05-01
EP0268654A1 (fr) 1988-06-01
KR880701458A (ko) 1988-07-27
JPS63503581A (ja) 1988-12-22

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