ATE462185T1 - Verfahren und vorrichtung zur lese-bitleitungs- klemmung für verstärkungszellen-dram-bausteine - Google Patents

Verfahren und vorrichtung zur lese-bitleitungs- klemmung für verstärkungszellen-dram-bausteine

Info

Publication number
ATE462185T1
ATE462185T1 AT04821590T AT04821590T ATE462185T1 AT E462185 T1 ATE462185 T1 AT E462185T1 AT 04821590 T AT04821590 T AT 04821590T AT 04821590 T AT04821590 T AT 04821590T AT E462185 T1 ATE462185 T1 AT E462185T1
Authority
AT
Austria
Prior art keywords
bit line
cell
gain cell
line clamping
reading bit
Prior art date
Application number
AT04821590T
Other languages
English (en)
Inventor
Toshiaki Kirihata
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE462185T1 publication Critical patent/ATE462185T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
AT04821590T 2003-08-26 2004-08-25 Verfahren und vorrichtung zur lese-bitleitungs- klemmung für verstärkungszellen-dram-bausteine ATE462185T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/604,911 US6831866B1 (en) 2003-08-26 2003-08-26 Method and apparatus for read bitline clamping for gain cell DRAM devices
PCT/US2004/027650 WO2005089086A2 (en) 2003-08-26 2004-08-25 Method and apparatus for read bitline clamping for gain cell dram devices

Publications (1)

Publication Number Publication Date
ATE462185T1 true ATE462185T1 (de) 2010-04-15

Family

ID=33490826

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04821590T ATE462185T1 (de) 2003-08-26 2004-08-25 Verfahren und vorrichtung zur lese-bitleitungs- klemmung für verstärkungszellen-dram-bausteine

Country Status (7)

Country Link
US (1) US6831866B1 (de)
EP (1) EP1665275B1 (de)
KR (1) KR100791367B1 (de)
CN (1) CN100429702C (de)
AT (1) ATE462185T1 (de)
DE (1) DE602004026204D1 (de)
WO (1) WO2005089086A2 (de)

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* Cited by examiner, † Cited by third party
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US7295474B2 (en) * 2005-06-30 2007-11-13 Intel Corporation Operating an information storage cell array
KR101475346B1 (ko) 2008-07-02 2014-12-23 삼성전자주식회사 비트라인 쌍의 디벨롭 레벨을 클립핑하는 디벨롭 레벨클리핑 회로, 이를 포함하는 컬럼 경로 회로 및 멀티 포트반도체 메모리 장치
US8027206B2 (en) * 2009-01-30 2011-09-27 Qualcomm Incorporated Bit line voltage control in spin transfer torque magnetoresistive random access memory
CN102612741B (zh) 2009-11-06 2014-11-12 株式会社半导体能源研究所 半导体装置
JP6012450B2 (ja) 2011-12-23 2016-10-25 株式会社半導体エネルギー研究所 半導体装置の駆動方法
CN103247331B (zh) 2012-02-13 2016-01-20 中国科学院微电子研究所 半导体存储器件及其访问方法
KR101362726B1 (ko) * 2012-03-13 2014-02-14 코아솔 주식회사 메모리 장치 및 그의 구동 방법
KR20140092537A (ko) 2013-01-16 2014-07-24 삼성전자주식회사 메모리 셀 및 이를 포함하는 메모리 장치
KR102168652B1 (ko) 2013-12-16 2020-10-23 삼성전자주식회사 감지 증폭기, 그것을 포함하는 반도체 메모리 장치 및 그것의 읽기 방법
US9691445B2 (en) 2014-05-01 2017-06-27 Bar-Ilan University Transistor gain cell with feedback
US10002660B2 (en) 2014-05-01 2018-06-19 Bar-Ilan University Transistor gain cell with feedback
DE102014115204B4 (de) * 2014-10-20 2020-08-20 Infineon Technologies Ag Testen von Vorrichtungen
US10431269B2 (en) * 2015-02-04 2019-10-01 Altera Corporation Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration
KR102817486B1 (ko) * 2024-04-03 2025-06-10 광운대학교 산학협력단 CIM 모델에서 XNOR과 AND 연산 구현이 가능한 4T 1C Gain eDRAM 셀

Family Cites Families (19)

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Publication number Priority date Publication date Assignee Title
US4417325A (en) * 1981-07-13 1983-11-22 Eliyahou Harari Highly scaleable dynamic ram cell with self-signal amplification
US4816706A (en) 1987-09-10 1989-03-28 International Business Machines Corporation Sense amplifier with improved bitline precharging for dynamic random access memory
US5132936A (en) * 1989-12-14 1992-07-21 Cypress Semiconductor Corporation MOS memory circuit with fast access time
JPH0492287A (ja) 1990-08-08 1992-03-25 Internatl Business Mach Corp <Ibm> ダイナミック・ランダム・アクセス・メモリ
US5253205A (en) * 1991-09-05 1993-10-12 Nippon Steel Semiconductor Corporation Bit line and cell plate clamp circuit for a DRAM
US5396452A (en) * 1993-07-02 1995-03-07 Wahlstrom; Sven E. Dynamic random access memory
US5390147A (en) 1994-03-02 1995-02-14 Atmel Corporation Core organization and sense amplifier having lubricating current, active clamping and buffered sense node for speed enhancement for non-volatile memory
US5521874A (en) 1994-12-14 1996-05-28 Sun Microsystems, Inc. High speed differential to single ended sense amplifier
US5923593A (en) * 1996-12-17 1999-07-13 Monolithic Systems, Inc. Multi-port DRAM cell and memory system using same
US5850366A (en) 1997-07-24 1998-12-15 Texas Instruments Incorporated Memory array having dummy cells implemented using standard array cells
EP0917203A3 (de) 1997-11-14 2003-02-05 Infineon Technologies AG Gain Cell DRAM Struktur und Verfahren zu deren Herstellung
US6317365B1 (en) * 1998-06-24 2001-11-13 Yamaha Corporation Semiconductor memory cell
JP2000113683A (ja) * 1998-10-02 2000-04-21 Hitachi Ltd 半導体装置
US5949720A (en) * 1998-10-30 1999-09-07 Stmicroelectronics, Inc. Voltage clamping method and apparatus for dynamic random access memory devices
US6282137B1 (en) 1999-09-14 2001-08-28 Agere Systems Guardian Corp. SRAM method and apparatus
US6407946B2 (en) * 1999-12-08 2002-06-18 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device
JP2001291389A (ja) 2000-03-31 2001-10-19 Hitachi Ltd 半導体集積回路
JP4164241B2 (ja) 2001-02-15 2008-10-15 株式会社ルネサステクノロジ 半導体装置
US6567330B2 (en) * 2001-08-17 2003-05-20 Kabushiki Kaisha Toshiba Semiconductor memory device

Also Published As

Publication number Publication date
WO2005089086A2 (en) 2005-09-29
EP1665275A2 (de) 2006-06-07
EP1665275B1 (de) 2010-03-24
US6831866B1 (en) 2004-12-14
KR100791367B1 (ko) 2008-01-07
CN1842843A (zh) 2006-10-04
DE602004026204D1 (de) 2010-05-06
WO2005089086A3 (en) 2006-02-09
EP1665275A4 (de) 2008-12-24
KR20060052884A (ko) 2006-05-19
CN100429702C (zh) 2008-10-29

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Legal Events

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