ATE464694T1 - Vorrichtung und verfahren zum automatischen selbstkalibrieren einer duty-cycle-schaltung für maximale chipleistungsfähigkeit - Google Patents
Vorrichtung und verfahren zum automatischen selbstkalibrieren einer duty-cycle-schaltung für maximale chipleistungsfähigkeitInfo
- Publication number
- ATE464694T1 ATE464694T1 AT06806822T AT06806822T ATE464694T1 AT E464694 T1 ATE464694 T1 AT E464694T1 AT 06806822 T AT06806822 T AT 06806822T AT 06806822 T AT06806822 T AT 06806822T AT E464694 T1 ATE464694 T1 AT E464694T1
- Authority
- AT
- Austria
- Prior art keywords
- dcc
- circuit
- built
- duty cycle
- setting
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3187—Built-in tests
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Dc-Dc Converters (AREA)
- Pulse Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/242,677 US7322001B2 (en) | 2005-10-04 | 2005-10-04 | Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance |
| PCT/EP2006/066739 WO2007039516A1 (en) | 2005-10-04 | 2006-09-26 | Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE464694T1 true ATE464694T1 (de) | 2010-04-15 |
Family
ID=37460149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT06806822T ATE464694T1 (de) | 2005-10-04 | 2006-09-26 | Vorrichtung und verfahren zum automatischen selbstkalibrieren einer duty-cycle-schaltung für maximale chipleistungsfähigkeit |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US7322001B2 (de) |
| EP (1) | EP1932235B1 (de) |
| JP (1) | JP4629778B2 (de) |
| KR (1) | KR101020394B1 (de) |
| CN (1) | CN101278481B (de) |
| AT (1) | ATE464694T1 (de) |
| DE (1) | DE602006013667D1 (de) |
| WO (1) | WO2007039516A1 (de) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7577859B2 (en) * | 2004-02-20 | 2009-08-18 | International Business Machines Corporation | System and method of controlling power consumption in an electronic system by applying a uniquely determined minimum operating voltage to an integrated circuit rather than a predetermined nominal voltage selected for a family of integrated circuits |
| US7322001B2 (en) * | 2005-10-04 | 2008-01-22 | International Business Machines Corporation | Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance |
| US7913199B2 (en) * | 2006-07-14 | 2011-03-22 | International Business Machines Corporation | Structure for a duty cycle correction circuit |
| US7417480B2 (en) * | 2006-07-14 | 2008-08-26 | International Business Machines Corporation | Duty cycle correction circuit whose operation is largely independent of operating voltage and process |
| KR100925364B1 (ko) * | 2007-02-13 | 2009-11-09 | 주식회사 하이닉스반도체 | 듀티 비를 보정하기 위한 클럭 변조 회로, 및 이를포함하는 스펙트럼 확산 클럭 발생 장치 |
| US7917785B2 (en) * | 2007-05-11 | 2011-03-29 | International Business Machines Corporation | Method of optimizing performance of multi-core chips and corresponding circuit and computer program product |
| WO2009001232A1 (en) * | 2007-06-22 | 2008-12-31 | Nxp B.V. | Method for in-system testing of communication systems |
| US8108813B2 (en) * | 2007-11-20 | 2012-01-31 | International Business Machines Corporation | Structure for a circuit obtaining desired phase locked loop duty cycle without pre-scaler |
| US20090128206A1 (en) * | 2007-11-20 | 2009-05-21 | Boerstler David W | Apparatus and Method for Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler |
| US8381143B2 (en) * | 2008-05-29 | 2013-02-19 | International Business Machines Corporation | Structure for a duty cycle correction circuit |
| KR100945797B1 (ko) * | 2008-05-30 | 2010-03-08 | 주식회사 하이닉스반도체 | 듀티 사이클 보정 회로 및 방법 |
| KR100933805B1 (ko) * | 2008-06-30 | 2009-12-24 | 주식회사 하이닉스반도체 | 듀티비 보정회로 및 그를 포함하는 지연고정루프회로 |
| US8181056B2 (en) * | 2008-09-30 | 2012-05-15 | Mosaid Technologies Incorporated | Serial-connected memory system with output delay adjustment |
| US8161313B2 (en) * | 2008-09-30 | 2012-04-17 | Mosaid Technologies Incorporated | Serial-connected memory system with duty cycle correction |
| DE102008059502A1 (de) * | 2008-11-28 | 2010-06-10 | Advanced Micro Devices, Inc., Sunnyvale | Kompensation der Leistungsbeeinträchtigung von Halbleiterbauelementen durch Anpassung des Tastgrades des Taktsignals |
| CN102035508B (zh) * | 2010-05-28 | 2016-01-20 | 上海华虹宏力半导体制造有限公司 | 一种时钟产生电路 |
| KR20130086423A (ko) * | 2012-01-25 | 2013-08-02 | 삼성전자주식회사 | 데이터 스트로브 신호의 듀티비 보정 방법 |
| US9484894B2 (en) | 2012-07-09 | 2016-11-01 | International Business Machines Corporation | Self-adjusting duty cycle tuner |
| US9319030B2 (en) | 2013-12-12 | 2016-04-19 | International Business Machines Corporation | Integrated circuit failure prediction using clock duty cycle recording and analysis |
| US9306547B2 (en) | 2013-12-12 | 2016-04-05 | International Business Machines Corporation | Duty cycle adjustment with error resiliency |
| GB2539459A (en) * | 2015-06-16 | 2016-12-21 | Nordic Semiconductor Asa | Waveform generation |
| CN107196656B (zh) * | 2016-03-15 | 2020-11-06 | 联发科技(新加坡)私人有限公司 | 一种信号校准电路及信号校准方法 |
| CN112204664B (zh) | 2018-05-29 | 2024-04-02 | 美光科技公司 | 用于设置用于改进时钟工作循环的工作循环调整器的设备及方法 |
| US10715127B2 (en) | 2018-11-21 | 2020-07-14 | Micron Technology, Inc. | Apparatuses and methods for using look-ahead duty cycle correction to determine duty cycle adjustment values while a semiconductor device remains in operation |
| US11189334B2 (en) | 2018-11-21 | 2021-11-30 | Micron Technology, Inc. | Apparatuses and methods for a multi-bit duty cycle monitor |
| CN113075531A (zh) * | 2021-03-24 | 2021-07-06 | 上海华虹宏力半导体制造有限公司 | 芯片的测试方法 |
Family Cites Families (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06249922A (ja) * | 1993-02-24 | 1994-09-09 | Matsushita Electric Ind Co Ltd | デューティサイクル制御装置 |
| JP3379209B2 (ja) * | 1994-03-16 | 2003-02-24 | 安藤電気株式会社 | クロックデューティ比自動調整回路 |
| US5757218A (en) * | 1996-03-12 | 1998-05-26 | International Business Machines Corporation | Clock signal duty cycle correction circuit and method |
| JP3688392B2 (ja) * | 1996-05-31 | 2005-08-24 | 三菱電機株式会社 | 波形整形装置およびクロック供給装置 |
| US5883523A (en) * | 1997-04-29 | 1999-03-16 | Credence Systems Corporation | Coherent switching power for an analog circuit tester |
| JPH1141925A (ja) * | 1997-07-24 | 1999-02-12 | Fujitsu Ltd | スイッチング電源 |
| US6363507B1 (en) * | 1998-10-19 | 2002-03-26 | Teradyne, Inc. | Integrated multi-channel analog test instrument architecture providing flexible triggering |
| US6535986B1 (en) * | 2000-03-14 | 2003-03-18 | International Business Machines Corporation | Optimizing performance of a clocked system by adjusting clock control settings and clock frequency |
| KR100366618B1 (ko) | 2000-03-31 | 2003-01-09 | 삼성전자 주식회사 | 클럭 신호의 듀티 사이클을 보정하는 지연 동기 루프 회로및 지연 동기 방법 |
| KR100360403B1 (ko) | 2000-04-10 | 2002-11-13 | 삼성전자 주식회사 | 듀티 싸이클 보정회로 및 방법 |
| US6452843B1 (en) * | 2000-12-19 | 2002-09-17 | Winbond Electronics Corporation | Method and apparatus for testing high-speed circuits based on slow-speed signals |
| JP2002216481A (ja) * | 2001-01-19 | 2002-08-02 | Hitachi Ltd | 半導体集積回路装置 |
| US6750689B2 (en) * | 2001-03-29 | 2004-06-15 | Intel Corporation | Method and apparatus for correcting a clock duty cycle in a clock distribution network |
| US6518809B1 (en) * | 2001-08-01 | 2003-02-11 | Cypress Semiconductor Corp. | Clock circuit with self correcting duty cycle |
| US6426660B1 (en) * | 2001-08-30 | 2002-07-30 | International Business Machines Corporation | Duty-cycle correction circuit |
| US6509766B1 (en) * | 2001-10-26 | 2003-01-21 | International Business Machines Corporation | Adjustable clock multiplier and method |
| US6593789B2 (en) * | 2001-12-14 | 2003-07-15 | International Business Machines Corporation | Precise and programmable duty cycle generator |
| KR100432883B1 (ko) * | 2001-12-18 | 2004-05-22 | 삼성전자주식회사 | 클럭 듀티/스큐 보정 기능을 갖는 위상 분주 회로 |
| US6583657B1 (en) * | 2002-06-20 | 2003-06-24 | International Business Machines Corporation | Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits |
| KR100486268B1 (ko) * | 2002-10-05 | 2005-05-03 | 삼성전자주식회사 | 내부에서 자체적으로 듀티싸이클 보정을 수행하는지연동기루프 회로 및 이의 듀티싸이클 보정방법 |
| US6967514B2 (en) * | 2002-10-21 | 2005-11-22 | Rambus, Inc. | Method and apparatus for digital duty cycle adjustment |
| JP2004185691A (ja) * | 2002-11-29 | 2004-07-02 | Nec Electronics Corp | 半導体記憶装置のテスト方法、半導体記憶装置のテスト回路、半導体記憶装置及び半導体装置 |
| JP4015937B2 (ja) * | 2002-12-06 | 2007-11-28 | 松下電器産業株式会社 | デューティ比補正回路 |
| KR100560660B1 (ko) * | 2003-03-28 | 2006-03-16 | 삼성전자주식회사 | 듀티 사이클 보정을 위한 장치 및 방법 |
| US6844766B2 (en) * | 2003-03-28 | 2005-01-18 | Infineon Technologies Ag | VCDL with linear delay characteristics and differential duty-cycle correction |
| KR100473813B1 (ko) * | 2003-07-10 | 2005-03-14 | 학교법인 포항공과대학교 | 다중 위상 클럭을 위한 디지털 듀티 사이클 보정 회로 및그 방법 |
| US6960952B2 (en) * | 2003-09-11 | 2005-11-01 | Rambus, Inc. | Configuring and selecting a duty cycle for an output driver |
| US7225092B2 (en) | 2004-10-21 | 2007-05-29 | International Business Machines Corporation | Method and apparatus for measuring and adjusting the duty cycle of a high speed clock |
| US7322001B2 (en) | 2005-10-04 | 2008-01-22 | International Business Machines Corporation | Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance |
-
2005
- 2005-10-04 US US11/242,677 patent/US7322001B2/en not_active Expired - Lifetime
-
2006
- 2006-09-26 EP EP06806822A patent/EP1932235B1/de active Active
- 2006-09-26 DE DE602006013667T patent/DE602006013667D1/de active Active
- 2006-09-26 WO PCT/EP2006/066739 patent/WO2007039516A1/en not_active Ceased
- 2006-09-26 AT AT06806822T patent/ATE464694T1/de not_active IP Right Cessation
- 2006-09-26 CN CN2006800367368A patent/CN101278481B/zh active Active
- 2006-09-26 KR KR1020087007983A patent/KR101020394B1/ko active Active
- 2006-09-26 JP JP2008533972A patent/JP4629778B2/ja active Active
-
2007
- 2007-08-31 US US11/848,314 patent/US7360135B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20070079197A1 (en) | 2007-04-05 |
| CN101278481B (zh) | 2012-06-27 |
| KR101020394B1 (ko) | 2011-03-09 |
| CN101278481A (zh) | 2008-10-01 |
| EP1932235A1 (de) | 2008-06-18 |
| WO2007039516A1 (en) | 2007-04-12 |
| JP4629778B2 (ja) | 2011-02-09 |
| US7360135B2 (en) | 2008-04-15 |
| US7322001B2 (en) | 2008-01-22 |
| EP1932235B1 (de) | 2010-04-14 |
| US20070300113A1 (en) | 2007-12-27 |
| DE602006013667D1 (de) | 2010-05-27 |
| KR20080056186A (ko) | 2008-06-20 |
| JP2009510793A (ja) | 2009-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ATE464694T1 (de) | Vorrichtung und verfahren zum automatischen selbstkalibrieren einer duty-cycle-schaltung für maximale chipleistungsfähigkeit | |
| DE602006007155D1 (de) | Verfahren und schaltung zur erzeugung eines referenzstroms zum lesen einer speicherzelle und vorrichtung damit | |
| ATE545887T1 (de) | Positive strahlungsempfindliche zusammensetzung und verfahren zur erzeugung eines musters mittels der strahlungsempfindlichen zusammensetzung | |
| ATE424566T1 (de) | Integrierte schaltung und verfahren zur gesicherten prüfung | |
| ATE390637T1 (de) | Verfahren und vorrichtung zum prüfen integrierter schaltungen | |
| ATE540520T1 (de) | Einrichtung und programm zur adressvergabe | |
| WO2002075336A3 (en) | Test system algorithmic program generators | |
| ATE447729T1 (de) | Verfahren zur bewertung der effekte von mehrfachbelichtungsprozessen in der lithographie | |
| ATE399331T1 (de) | Verfahren und vorrichtung für eingebetteten eingebauten selbsttest (bist) elektronischer schaltungen und systeme | |
| SG129366A1 (en) | Method of selecting a grid model for correcting a process recipe for grid deformations in a lithographic apparatus and lithographic assembly using thesame | |
| TW200504748A (en) | Memory having variable refresh control and method therefor | |
| WO2008088992A3 (en) | Method for enhancing the diagnostic accuracy of a vlsi chip | |
| TW200608032A (en) | Method and apparatus for configuration of automated debug of in-circuit tests | |
| ATE485564T1 (de) | System und verfahren zur verwendung einer modellanalyse zum erzeugen gerichteter prüfvektoren | |
| WO2008010608A3 (en) | Signal analyzer and method for signal analysis | |
| TWI368740B (en) | Probe card,method of making the same and test environment for testing integrated circuits | |
| ATE520037T1 (de) | Verfahren zur überwachung und anpassung einer schaltungsleistung | |
| ATE268025T1 (de) | Vorrichtung und verfahren für leistungs- und fehlerdatenanalyse | |
| TW200724949A (en) | Test sequence optimization method and design tool | |
| DE60318452D1 (de) | Welllenformerzeugungsverfahren, wellenformerzeugungsprogramm, wellenformerzeugungsschaltung und radareinrichtung | |
| DE60314955D1 (de) | Verfahren zur Inspektion von Dampfturbinen | |
| NO20090384L (no) | Fremgangsmåte og apparat for formasjonstesting | |
| ATE531131T1 (de) | Verfahren und vorrichtung zum verteilen mehrerer signaleingänge an mehrere integrierte schaltungen | |
| WO2008114671A1 (ja) | 試験装置、電子デバイスおよび試験方法 | |
| TW200636272A (en) | Test equipment, test method, manufacturing method of electronic device, test simulator, and test simulation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |