ATE491209T1 - Verfahren und system zur minimierung der auswirkung von aktualisierungsoperationen auf die leistung eines nichtflüchtigen speichers - Google Patents

Verfahren und system zur minimierung der auswirkung von aktualisierungsoperationen auf die leistung eines nichtflüchtigen speichers

Info

Publication number
ATE491209T1
ATE491209T1 AT05824687T AT05824687T ATE491209T1 AT E491209 T1 ATE491209 T1 AT E491209T1 AT 05824687 T AT05824687 T AT 05824687T AT 05824687 T AT05824687 T AT 05824687T AT E491209 T1 ATE491209 T1 AT E491209T1
Authority
AT
Austria
Prior art keywords
volatile memory
minimizing
effect
memory performance
update operations
Prior art date
Application number
AT05824687T
Other languages
English (en)
Inventor
Robert Walker
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE491209T1 publication Critical patent/ATE491209T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Stored Programmes (AREA)
AT05824687T 2004-11-24 2005-11-22 Verfahren und system zur minimierung der auswirkung von aktualisierungsoperationen auf die leistung eines nichtflüchtigen speichers ATE491209T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/997,138 US7930471B2 (en) 2004-11-24 2004-11-24 Method and system for minimizing impact of refresh operations on volatile memory performance
PCT/US2005/042535 WO2006058118A1 (en) 2004-11-24 2005-11-22 Method and system for minimizing impact of refresh operations on volatile memory performance

Publications (1)

Publication Number Publication Date
ATE491209T1 true ATE491209T1 (de) 2010-12-15

Family

ID=36123458

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05824687T ATE491209T1 (de) 2004-11-24 2005-11-22 Verfahren und system zur minimierung der auswirkung von aktualisierungsoperationen auf die leistung eines nichtflüchtigen speichers

Country Status (13)

Country Link
US (2) US7930471B2 (de)
EP (1) EP1815479B1 (de)
JP (2) JP5001165B2 (de)
KR (2) KR101049312B1 (de)
CN (2) CN101103415B (de)
AT (1) ATE491209T1 (de)
BR (1) BRPI0518259B1 (de)
DE (1) DE602005025243D1 (de)
ES (1) ES2355737T3 (de)
IL (1) IL183416A (de)
PL (1) PL1815479T3 (de)
TW (1) TWI402841B (de)
WO (1) WO2006058118A1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7930471B2 (en) * 2004-11-24 2011-04-19 Qualcomm Incorporated Method and system for minimizing impact of refresh operations on volatile memory performance
US7590021B2 (en) * 2007-07-26 2009-09-15 Qualcomm Incorporated System and method to reduce dynamic RAM power consumption via the use of valid data indicators
US7965532B2 (en) * 2007-08-28 2011-06-21 Micron Technology, Inc. Enhanced performance memory systems and methods
US8347027B2 (en) * 2009-11-05 2013-01-01 Honeywell International Inc. Reducing power consumption for dynamic memories using distributed refresh control
US8392650B2 (en) * 2010-04-01 2013-03-05 Intel Corporation Fast exit from self-refresh state of a memory device
JP2013157047A (ja) * 2012-01-27 2013-08-15 Toshiba Corp 磁気ディスク装置及び同装置におけるデータリフレッシュ方法
KR20130129786A (ko) 2012-05-21 2013-11-29 에스케이하이닉스 주식회사 리프래쉬 방법과 이를 이용한 반도체 메모리 장치
JP5917307B2 (ja) 2012-06-11 2016-05-11 ルネサスエレクトロニクス株式会社 メモリコントローラ、揮発性メモリの制御方法及びメモリ制御システム
KR102023487B1 (ko) 2012-09-17 2019-09-20 삼성전자주식회사 오토 리프레쉬 커맨드를 사용하지 않고 리프레쉬를 수행할 수 있는 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
US20150294711A1 (en) * 2012-10-22 2015-10-15 Hewlett-Packard Development Company, L.P. Performing refresh of a memory device in response to access of data
KR102107470B1 (ko) * 2013-02-07 2020-05-07 삼성전자주식회사 메모리 장치 및 메모리 장치의 리프레시 방법
US20160239442A1 (en) * 2015-02-13 2016-08-18 Qualcomm Incorporated Scheduling volatile memory maintenance events in a multi-processor system
KR102304928B1 (ko) * 2015-05-13 2021-09-27 삼성전자 주식회사 리프레시 명령을 분산시키는 메모리 장치 및 상기 장치를 포함하는 메모리 시스템
KR102326018B1 (ko) 2015-08-24 2021-11-12 삼성전자주식회사 메모리 시스템
KR102373544B1 (ko) 2015-11-06 2022-03-11 삼성전자주식회사 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
CN106601286A (zh) * 2016-12-20 2017-04-26 湖南国科微电子股份有限公司 DDRx SDRAM存储器刷新方法及存储器控制器
CN107527648A (zh) * 2017-09-04 2017-12-29 珠海市杰理科技股份有限公司 存储器的刷新方法和系统
CN110556139B (zh) * 2018-05-31 2021-06-18 联发科技股份有限公司 用以控制存储器的电路及相关的方法
US10777252B2 (en) 2018-08-22 2020-09-15 Apple Inc. System and method for performing per-bank memory refresh
CN110299164B (zh) * 2019-06-28 2021-10-26 西安紫光国芯半导体有限公司 一种自适应dram刷新控制方法和dram刷新控制器
KR20230133031A (ko) 2022-03-10 2023-09-19 에스케이하이닉스 주식회사 리프레쉬 제어 장치를 포함하는 메모리 장치 및 메모리 시스템
KR20240059151A (ko) 2022-10-27 2024-05-07 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0164735A3 (de) * 1984-06-11 1988-11-09 Nec Corporation Mikroprozessor mit Erfrischungsschaltung für dynamischen Speicher
JPS61160897A (ja) * 1984-12-31 1986-07-21 Fujitsu Ltd ダイナミツク形ｒａｍのリフレツシユ方式
US4984209A (en) 1987-10-30 1991-01-08 Zenith Data Systems Corporation Burst refresh of dynamic random access memory for personal computers
JPH01267896A (ja) 1988-04-19 1989-10-25 Toshiba Corp 半導体メモリ
JPH01307997A (ja) 1988-06-06 1989-12-12 Toshiba Corp メモリ装置
JPH0349094A (ja) * 1989-07-18 1991-03-01 Toshiba Corp メモリ制御装置
JPH0434792A (ja) 1990-05-30 1992-02-05 Ricoh Co Ltd Ｄｒａｍ制御方式
EP0547758B1 (de) 1991-12-18 1999-01-20 Sun Microsystems, Inc. Wahlfreie Auffrischung
JPH06236683A (ja) 1993-02-09 1994-08-23 Oki Electric Ind Co Ltd メモリリフレッシュ制御回路
US5873114A (en) * 1995-08-18 1999-02-16 Advanced Micro Devices, Inc. Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles
JPH10106259A (ja) 1996-09-26 1998-04-24 Nec Gumma Ltd メモリ制御装置
JPH10199236A (ja) * 1997-01-16 1998-07-31 Matsushita Electric Ind Co Ltd Ｄｒａｍコントローラ
US5907857A (en) 1997-04-07 1999-05-25 Opti, Inc. Refresh-ahead and burst refresh preemption technique for managing DRAM in computer system
US6272588B1 (en) * 1997-05-30 2001-08-07 Motorola Inc. Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry
US20020069319A1 (en) * 2000-12-01 2002-06-06 Ming-Hsien Lee Method and apparatus of event-driven based refresh for high performance memory controller
JP2005310245A (ja) * 2004-04-20 2005-11-04 Seiko Epson Corp メモリコントローラ、半導体集積回路装置、マイクロコンピュータ及び電子機器
US7930471B2 (en) 2004-11-24 2011-04-19 Qualcomm Incorporated Method and system for minimizing impact of refresh operations on volatile memory performance

Also Published As

Publication number Publication date
CN102969017B (zh) 2016-01-06
PL1815479T3 (pl) 2011-05-31
US7930471B2 (en) 2011-04-19
KR101049312B1 (ko) 2011-07-13
TW200632909A (en) 2006-09-16
IL183416A (en) 2012-10-31
WO2006058118A1 (en) 2006-06-01
IL183416A0 (en) 2007-09-20
CN101103415A (zh) 2008-01-09
JP2011018435A (ja) 2011-01-27
JP2008522339A (ja) 2008-06-26
DE602005025243D1 (de) 2011-01-20
EP1815479A1 (de) 2007-08-08
TWI402841B (zh) 2013-07-21
KR20090071672A (ko) 2009-07-01
CN102969017A (zh) 2013-03-13
US20110161579A1 (en) 2011-06-30
US20060112217A1 (en) 2006-05-25
BRPI0518259B1 (pt) 2017-12-26
ES2355737T3 (es) 2011-03-30
KR20070086505A (ko) 2007-08-27
HK1110987A1 (en) 2008-07-25
EP1815479B1 (de) 2010-12-08
US8171211B2 (en) 2012-05-01
HK1179046A1 (zh) 2013-09-19
CN101103415B (zh) 2012-12-12
JP5001165B2 (ja) 2012-08-15
JP5627953B2 (ja) 2014-11-19
BRPI0518259A2 (pt) 2008-11-11

Similar Documents

Publication Publication Date Title
ATE491209T1 (de) Verfahren und system zur minimierung der auswirkung von aktualisierungsoperationen auf die leistung eines nichtflüchtigen speichers
DE60310676D1 (de) System und verfahren zum identifizieren eines drahtlosen versorgungsknotens für eine mobileinheit
TW200623122A (en) Refreshing dynamic volatile memory
NO20053075D0 (no) System og fremgangsmate for tilgangskontroll pa detaljniva pa data lagret i relasjonale databaser.
DE602005000669D1 (de) System und Verfahren zur dynamischen Planung von Aufgaben in Abhängigkeit von der Position eines mobilen Benutzers
TW200506604A (en) Self-refresh apparatus and method
MX2010012833A (es) Dispositivo de supervision de cepillo de dientes.
ATE528763T1 (de) System und verfahren zur verringerung des dynamischen ram-energieverbrauchs durch verwenden von gültigen datenmarkern
GB2447155A (en) Mechanism for self refresh during C0
ATE517417T1 (de) Durch software aufgefrischte speichereinrichtung und verfahren
EP2345204A4 (de) System und verfahren zur dynamischen bereitstellung
EP2285150A4 (de) Verfahren, system und einrichtung zum melden von benutzerstandortinformationen
DE502004006864D1 (de) Verfahren zur computergestützten simulation einer maschinenanordnung, simulationseinrichtung, computerlesbares speichermedium und computerprogramm-element
TW200707190A (en) Partial page scheme for memory technologies
TW200641891A (en) System and method for hidden-refresh pate modification
ATE518191T1 (de) Speicherabbildungssystem, anforderungssteuerung, mehrfach-verarbeitungsanordnung, zentrale interrput-request-steuerung, vorrichtung, verfahren zur steuerung des speicherzugriffs und computerprogrammprodukt
ATE481672T1 (de) Verfahren zum aufrechterhalten eines usb- aktivzustands ohne datentransfer
NO20082456L (no) Fremgangsmate for a lagre posisjonen til et parkert kjoretoy og navigasjonsinnretning anordnet for dette
ATE534422T1 (de) Vorrichtung zur beurteilung von schlaflosigkeit und zur automatisierten modifizierung des schlafverhaltens
BR112012026396A2 (pt) método de gerenciar um programa de premiação a motorista e um sistema para o mesmo
ATE342958T1 (de) Verbessertes rollflaschesystem zur kultivierung von zellen und gewebe
TW200943173A (en) Display control device with automatic firmware update and update method thereof
EP4542533A4 (de) Anzeigetafelkompensationsverfahren und -vorrichtung, vorrichtung und speichermedium
ITTO20050735A1 (it) Metodo per concatenare eventi in un registro cronologico di eventi di sistema
DE60331884D1 (de) Kommunikationssystem und -verfahren, das gegen Burstfehler unempfindlich ist, Rechnerprogramm zur Durchführung des Verfahrens, und rechnerlesbares Medium zum Speichern des Programms

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties