BRPI0518259A2 - mÉtodo e sistema para minimizar impacto de operaÇÕes de renovaÇço no desempenho de memària volÁtil - Google Patents

mÉtodo e sistema para minimizar impacto de operaÇÕes de renovaÇço no desempenho de memària volÁtil

Info

Publication number
BRPI0518259A2
BRPI0518259A2 BRPI0518259-0A BRPI0518259A BRPI0518259A2 BR PI0518259 A2 BRPI0518259 A2 BR PI0518259A2 BR PI0518259 A BRPI0518259 A BR PI0518259A BR PI0518259 A2 BRPI0518259 A2 BR PI0518259A2
Authority
BR
Brazil
Prior art keywords
volatile memory
memory performance
minimizing impact
renewal operations
refresh
Prior art date
Application number
BRPI0518259-0A
Other languages
English (en)
Inventor
Robert Michael Walker
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI0518259A2 publication Critical patent/BRPI0518259A2/pt
Publication of BRPI0518259B1 publication Critical patent/BRPI0518259B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Stored Programmes (AREA)

Abstract

MÉTODO E SISTEMA PARA MINIMIZAR IMPACTO DE OPERAÇÕES DE RENOVAÇAO NO DESEMPENHO DE MEMàRIA VOLÁTIL. Um sistema de memória é provido. O sistema inclui uma memoria volátil, um contador de renovação configurado para monitorar um número de renovações avançadas realizadas na memória volátil, e um controlador configurado para verificar o contador de renovação para determinar se uma renovação programada regularmente pode ser pulada em resposta à detecção de uma solicitação para a renovação programada regularmente.
BRPI0518259-0A 2004-11-24 2005-11-22 Method and system for minimizing impact of renewal operations in volatile memory performance BRPI0518259B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/997,138 US7930471B2 (en) 2004-11-24 2004-11-24 Method and system for minimizing impact of refresh operations on volatile memory performance
US10/997,138 2004-11-24
PCT/US2005/042535 WO2006058118A1 (en) 2004-11-24 2005-11-22 Method and system for minimizing impact of refresh operations on volatile memory performance

Publications (2)

Publication Number Publication Date
BRPI0518259A2 true BRPI0518259A2 (pt) 2008-11-11
BRPI0518259B1 BRPI0518259B1 (pt) 2017-12-26

Family

ID=36123458

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0518259-0A BRPI0518259B1 (pt) 2004-11-24 2005-11-22 Method and system for minimizing impact of renewal operations in volatile memory performance

Country Status (13)

Country Link
US (2) US7930471B2 (pt)
EP (1) EP1815479B1 (pt)
JP (2) JP5001165B2 (pt)
KR (2) KR101049312B1 (pt)
CN (2) CN101103415B (pt)
AT (1) ATE491209T1 (pt)
BR (1) BRPI0518259B1 (pt)
DE (1) DE602005025243D1 (pt)
ES (1) ES2355737T3 (pt)
IL (1) IL183416A (pt)
PL (1) PL1815479T3 (pt)
TW (1) TWI402841B (pt)
WO (1) WO2006058118A1 (pt)

Families Citing this family (22)

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US7930471B2 (en) * 2004-11-24 2011-04-19 Qualcomm Incorporated Method and system for minimizing impact of refresh operations on volatile memory performance
US7590021B2 (en) * 2007-07-26 2009-09-15 Qualcomm Incorporated System and method to reduce dynamic RAM power consumption via the use of valid data indicators
US7965532B2 (en) * 2007-08-28 2011-06-21 Micron Technology, Inc. Enhanced performance memory systems and methods
US8347027B2 (en) * 2009-11-05 2013-01-01 Honeywell International Inc. Reducing power consumption for dynamic memories using distributed refresh control
US8392650B2 (en) * 2010-04-01 2013-03-05 Intel Corporation Fast exit from self-refresh state of a memory device
JP2013157047A (ja) * 2012-01-27 2013-08-15 Toshiba Corp 磁気ディスク装置及び同装置におけるデータリフレッシュ方法
KR20130129786A (ko) 2012-05-21 2013-11-29 에스케이하이닉스 주식회사 리프래쉬 방법과 이를 이용한 반도체 메모리 장치
JP5917307B2 (ja) 2012-06-11 2016-05-11 ルネサスエレクトロニクス株式会社 メモリコントローラ、揮発性メモリの制御方法及びメモリ制御システム
KR102023487B1 (ko) 2012-09-17 2019-09-20 삼성전자주식회사 오토 리프레쉬 커맨드를 사용하지 않고 리프레쉬를 수행할 수 있는 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
US20150294711A1 (en) * 2012-10-22 2015-10-15 Hewlett-Packard Development Company, L.P. Performing refresh of a memory device in response to access of data
KR102107470B1 (ko) * 2013-02-07 2020-05-07 삼성전자주식회사 메모리 장치 및 메모리 장치의 리프레시 방법
US20160239442A1 (en) * 2015-02-13 2016-08-18 Qualcomm Incorporated Scheduling volatile memory maintenance events in a multi-processor system
KR102304928B1 (ko) * 2015-05-13 2021-09-27 삼성전자 주식회사 리프레시 명령을 분산시키는 메모리 장치 및 상기 장치를 포함하는 메모리 시스템
KR102326018B1 (ko) 2015-08-24 2021-11-12 삼성전자주식회사 메모리 시스템
KR102373544B1 (ko) 2015-11-06 2022-03-11 삼성전자주식회사 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
CN106601286A (zh) * 2016-12-20 2017-04-26 湖南国科微电子股份有限公司 DDRx SDRAM存储器刷新方法及存储器控制器
CN107527648A (zh) * 2017-09-04 2017-12-29 珠海市杰理科技股份有限公司 存储器的刷新方法和系统
CN110556139B (zh) * 2018-05-31 2021-06-18 联发科技股份有限公司 用以控制存储器的电路及相关的方法
US10777252B2 (en) 2018-08-22 2020-09-15 Apple Inc. System and method for performing per-bank memory refresh
CN110299164B (zh) * 2019-06-28 2021-10-26 西安紫光国芯半导体有限公司 一种自适应dram刷新控制方法和dram刷新控制器
KR20230133031A (ko) 2022-03-10 2023-09-19 에스케이하이닉스 주식회사 리프레쉬 제어 장치를 포함하는 메모리 장치 및 메모리 시스템
KR20240059151A (ko) 2022-10-27 2024-05-07 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법

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EP0164735A3 (en) * 1984-06-11 1988-11-09 Nec Corporation A microprocessor having a dynamic memory refresh circuit
JPS61160897A (ja) * 1984-12-31 1986-07-21 Fujitsu Ltd ダイナミツク形ｒａｍのリフレツシユ方式
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JPH01267896A (ja) 1988-04-19 1989-10-25 Toshiba Corp 半導体メモリ
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JPH10106259A (ja) 1996-09-26 1998-04-24 Nec Gumma Ltd メモリ制御装置
JPH10199236A (ja) * 1997-01-16 1998-07-31 Matsushita Electric Ind Co Ltd Ｄｒａｍコントローラ
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US6272588B1 (en) * 1997-05-30 2001-08-07 Motorola Inc. Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry
US20020069319A1 (en) * 2000-12-01 2002-06-06 Ming-Hsien Lee Method and apparatus of event-driven based refresh for high performance memory controller
JP2005310245A (ja) * 2004-04-20 2005-11-04 Seiko Epson Corp メモリコントローラ、半導体集積回路装置、マイクロコンピュータ及び電子機器
US7930471B2 (en) 2004-11-24 2011-04-19 Qualcomm Incorporated Method and system for minimizing impact of refresh operations on volatile memory performance

Also Published As

Publication number Publication date
CN102969017B (zh) 2016-01-06
PL1815479T3 (pl) 2011-05-31
US7930471B2 (en) 2011-04-19
KR101049312B1 (ko) 2011-07-13
TW200632909A (en) 2006-09-16
IL183416A (en) 2012-10-31
WO2006058118A1 (en) 2006-06-01
IL183416A0 (en) 2007-09-20
CN101103415A (zh) 2008-01-09
JP2011018435A (ja) 2011-01-27
JP2008522339A (ja) 2008-06-26
DE602005025243D1 (de) 2011-01-20
EP1815479A1 (en) 2007-08-08
TWI402841B (zh) 2013-07-21
ATE491209T1 (de) 2010-12-15
KR20090071672A (ko) 2009-07-01
CN102969017A (zh) 2013-03-13
US20110161579A1 (en) 2011-06-30
US20060112217A1 (en) 2006-05-25
BRPI0518259B1 (pt) 2017-12-26
ES2355737T3 (es) 2011-03-30
KR20070086505A (ko) 2007-08-27
HK1110987A1 (en) 2008-07-25
EP1815479B1 (en) 2010-12-08
US8171211B2 (en) 2012-05-01
HK1179046A1 (zh) 2013-09-19
CN101103415B (zh) 2012-12-12
JP5001165B2 (ja) 2012-08-15
JP5627953B2 (ja) 2014-11-19

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Legal Events

Date Code Title Description
B15K Others concerning applications: alteration of classification

Ipc: G06F 13/16 (2006.01), G11C 11/406 (2006.01)

B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 26/12/2017, OBSERVADAS AS CONDICOES LEGAIS.