ATE521984T1 - Herstellungsverfahren von gestapelten und selbstausgerichteten komponenten auf einem substrat - Google Patents

Herstellungsverfahren von gestapelten und selbstausgerichteten komponenten auf einem substrat

Info

Publication number
ATE521984T1
ATE521984T1 AT09172758T AT09172758T ATE521984T1 AT E521984 T1 ATE521984 T1 AT E521984T1 AT 09172758 T AT09172758 T AT 09172758T AT 09172758 T AT09172758 T AT 09172758T AT E521984 T1 ATE521984 T1 AT E521984T1
Authority
AT
Austria
Prior art keywords
substrate
resin
monocrystalline silicon
components
zones
Prior art date
Application number
AT09172758T
Other languages
English (en)
Inventor
Romain Wacquez
Philippe Coronel
Vincent Destefanis
Jean-Michel Hartmann
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE521984T1 publication Critical patent/ATE521984T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Micromachines (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Magnetic Heads (AREA)
  • Formation Of Insulating Films (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
AT09172758T 2008-10-17 2009-10-12 Herstellungsverfahren von gestapelten und selbstausgerichteten komponenten auf einem substrat ATE521984T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0857060A FR2937463B1 (fr) 2008-10-17 2008-10-17 Procede de fabrication de composants empiles et auto-alignes sur un substrat

Publications (1)

Publication Number Publication Date
ATE521984T1 true ATE521984T1 (de) 2011-09-15

Family

ID=40651428

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09172758T ATE521984T1 (de) 2008-10-17 2009-10-12 Herstellungsverfahren von gestapelten und selbstausgerichteten komponenten auf einem substrat

Country Status (5)

Country Link
US (1) US8110460B2 (de)
EP (1) EP2178111B1 (de)
JP (1) JP2010098319A (de)
AT (1) ATE521984T1 (de)
FR (1) FR2937463B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2953991B1 (fr) * 2009-12-10 2012-01-06 Commissariat Energie Atomique Procede de realisation d'un revetement de surface controle tridimensionnellement dans une cavite
US8361907B2 (en) * 2010-05-10 2013-01-29 International Business Machines Corporation Directionally etched nanowire field effect transistors
FR2989515B1 (fr) 2012-04-16 2015-01-16 Commissariat Energie Atomique Procede ameliore de realisation d'une structure de transistor a nano-fils superposes et a grille enrobante
FR3037716B1 (fr) * 2015-06-18 2018-06-01 Commissariat A L'energie Atomique Et Aux Energies Alternatives Transistors superposes avec zone active du transistor superieur auto-alignee

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2838238B1 (fr) * 2002-04-08 2005-04-15 St Microelectronics Sa Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant
US7015147B2 (en) * 2003-07-22 2006-03-21 Sharp Laboratories Of America, Inc. Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer
FR2858876B1 (fr) 2003-08-12 2006-03-03 St Microelectronics Sa Procede de formation sous une couche mince d'un premier materiau de portions d'un autre materiau et/ou de zones de vide
KR100626372B1 (ko) * 2004-04-09 2006-09-20 삼성전자주식회사 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 제조 방법
KR101172853B1 (ko) * 2005-07-22 2012-08-10 삼성전자주식회사 반도체 소자의 형성 방법
FR2893762B1 (fr) 2005-11-18 2007-12-21 Commissariat Energie Atomique Procede de realisation de transistor a double grilles auto-alignees par reduction de motifs de grille
FR2897201B1 (fr) * 2006-02-03 2008-04-25 Stmicroelectronics Crolles Sas Dispositif de transistor a doubles grilles planaires et procede de fabrication.
FR2897471A1 (fr) 2006-02-10 2007-08-17 St Microelectronics Sa Formation d'une portion de couche semiconductrice monocristalline separee d'un substrat
US7776745B2 (en) * 2006-02-10 2010-08-17 Stmicroelectronics S.A. Method for etching silicon-germanium in the presence of silicon

Also Published As

Publication number Publication date
EP2178111B1 (de) 2011-08-24
EP2178111A1 (de) 2010-04-21
JP2010098319A (ja) 2010-04-30
US20100099233A1 (en) 2010-04-22
FR2937463B1 (fr) 2010-12-24
US8110460B2 (en) 2012-02-07
FR2937463A1 (fr) 2010-04-23

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