ATE358889T1 - Verfahren zur herstellung einer plattenförmigen struktur insbesondere aus silizium, verwendung des verfahrens und der so hergestellten plattenförmigen struktur insbesondere aus silizium - Google Patents
Verfahren zur herstellung einer plattenförmigen struktur insbesondere aus silizium, verwendung des verfahrens und der so hergestellten plattenförmigen struktur insbesondere aus siliziumInfo
- Publication number
- ATE358889T1 ATE358889T1 AT04787425T AT04787425T ATE358889T1 AT E358889 T1 ATE358889 T1 AT E358889T1 AT 04787425 T AT04787425 T AT 04787425T AT 04787425 T AT04787425 T AT 04787425T AT E358889 T1 ATE358889 T1 AT E358889T1
- Authority
- AT
- Austria
- Prior art keywords
- plate
- silicon
- shaped structure
- molecules
- intermediate layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
- H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
- H10P10/126—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates characterised by the composition of the bonding layer, e.g. dopant concentration or stoichiometry
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Thermal Sciences (AREA)
- Element Separation (AREA)
- Silicon Compounds (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Surface Treatment Of Glass (AREA)
- Laminated Bodies (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0311450A FR2860249B1 (fr) | 2003-09-30 | 2003-09-30 | Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE358889T1 true ATE358889T1 (de) | 2007-04-15 |
Family
ID=34307284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT04787425T ATE358889T1 (de) | 2003-09-30 | 2004-09-23 | Verfahren zur herstellung einer plattenförmigen struktur insbesondere aus silizium, verwendung des verfahrens und der so hergestellten plattenförmigen struktur insbesondere aus silizium |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US8062564B2 (de) |
| EP (1) | EP1671361B1 (de) |
| JP (1) | JP4932485B2 (de) |
| KR (1) | KR101044503B1 (de) |
| CN (1) | CN100514560C (de) |
| AT (1) | ATE358889T1 (de) |
| DE (1) | DE602004005731T2 (de) |
| FR (1) | FR2860249B1 (de) |
| WO (1) | WO2005034218A2 (de) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7018909B2 (en) * | 2003-02-28 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Forming structures that include a relaxed or pseudo-relaxed layer on a substrate |
| US8475693B2 (en) | 2003-09-30 | 2013-07-02 | Soitec | Methods of making substrate structures having a weakened intermediate layer |
| FR2865574B1 (fr) * | 2004-01-26 | 2006-04-07 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat demontable |
| EP1831922B9 (de) * | 2004-12-28 | 2010-02-24 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von löchern |
| FR2895420B1 (fr) * | 2005-12-27 | 2008-02-22 | Tracit Technologies Sa | Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede. |
| FR2902699B1 (fr) | 2006-06-26 | 2010-10-22 | Skf Ab | Dispositif de butee de suspension et jambe de force. |
| FR2906587B1 (fr) | 2006-10-03 | 2009-07-10 | Skf Ab | Dispositif de galet tendeur. |
| ATE544594T1 (de) * | 2006-12-22 | 2012-02-15 | Telecom Italia Spa | Tintenstrahldruckkopfherstellungsverfahren |
| FR2913081B1 (fr) | 2007-02-27 | 2009-05-15 | Skf Ab | Dispositif de poulie debrayable |
| FR2913968B1 (fr) | 2007-03-23 | 2009-06-12 | Soitec Silicon On Insulator | Procede de realisation de membranes autoportees. |
| FR2926672B1 (fr) | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication de couches de materiau epitaxie |
| FR2926674B1 (fr) * | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable |
| FR2931293B1 (fr) | 2008-05-15 | 2010-09-03 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante |
| TWI457984B (zh) | 2008-08-06 | 2014-10-21 | S O I Tec絕緣層上矽科技公司 | 應變層的鬆弛方法 |
| EP2151856A1 (de) | 2008-08-06 | 2010-02-10 | S.O.I. TEC Silicon | Relaxation von Spannungsschichten |
| EP2151861A1 (de) | 2008-08-06 | 2010-02-10 | S.O.I. TEC Silicon | Passivierung von geätzten Halbleiterstrukturen |
| EP2151852B1 (de) | 2008-08-06 | 2020-01-15 | Soitec | Relaxation und Übertragung von Spannungsschichten |
| EP2159836B1 (de) | 2008-08-25 | 2017-05-31 | Soitec | Versteifungsschichten zur Relaxation von verspannten Schichten |
| FR2942073B1 (fr) | 2009-02-10 | 2011-04-29 | Soitec Silicon On Insulator | Procede de realisation d'une couche de cavites |
| FR2963982B1 (fr) | 2010-08-20 | 2012-09-28 | Soitec Silicon On Insulator | Procede de collage a basse temperature |
| FR2965396B1 (fr) * | 2010-09-29 | 2013-02-22 | S O I Tec Silicon On Insulator Tech | Substrat démontable, procédés de fabrication et de démontage d'un tel substrat |
| FR2978600B1 (fr) | 2011-07-25 | 2014-02-07 | Soitec Silicon On Insulator | Procede et dispositif de fabrication de couche de materiau semi-conducteur |
| FR2992464B1 (fr) * | 2012-06-26 | 2015-04-03 | Soitec Silicon On Insulator | Procede de transfert d'une couche |
| US9875935B2 (en) * | 2013-03-08 | 2018-01-23 | Infineon Technologies Austria Ag | Semiconductor device and method for producing the same |
| CN103779372A (zh) * | 2014-02-10 | 2014-05-07 | 中国电子科技集团公司第四十四研究所 | 基于非本征吸杂技术的ccd制作工艺 |
| WO2016071064A1 (en) * | 2014-11-07 | 2016-05-12 | Abb Technology Ag | Semiconductor device manufacturing method using a sealing layer for sealing of a gap between two wafers bonded to each other |
| US10124338B2 (en) * | 2014-11-19 | 2018-11-13 | Imec Vzw | Microbubble generator device, systems and method to fabricate |
| FR3029538B1 (fr) * | 2014-12-04 | 2019-04-26 | Soitec | Procede de transfert de couche |
| FR3117666B1 (fr) * | 2020-12-15 | 2022-10-28 | Commissariat Energie Atomique | Procede de fabrication d’une structure semi-conductrice comprenant une zone d’interface incluant des agglomerats |
| US20240091995A1 (en) * | 2022-09-14 | 2024-03-21 | University Of Washington | Methods and systems for forming microcellular bubbles in selected portion of a thermoplastic member |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4979015A (en) * | 1987-01-28 | 1990-12-18 | Texas Instruments Incorporated | Insulated substrate for flip-chip integrated circuit device |
| JPH0851103A (ja) * | 1994-08-08 | 1996-02-20 | Fuji Electric Co Ltd | 薄膜の生成方法 |
| JP2666757B2 (ja) * | 1995-01-09 | 1997-10-22 | 日本電気株式会社 | Soi基板の製造方法 |
| CN1132223C (zh) * | 1995-10-06 | 2003-12-24 | 佳能株式会社 | 半导体衬底及其制造方法 |
| US6127285A (en) * | 1997-02-28 | 2000-10-03 | Dallas Instruments Incorporated | Interlevel dielectrics with reduced dielectric constant |
| FR2767416B1 (fr) * | 1997-08-12 | 1999-10-01 | Commissariat Energie Atomique | Procede de fabrication d'un film mince de materiau solide |
| FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
| JP4075021B2 (ja) * | 1997-12-26 | 2008-04-16 | ソニー株式会社 | 半導体基板の製造方法および薄膜半導体部材の製造方法 |
| JPH11233449A (ja) * | 1998-02-13 | 1999-08-27 | Denso Corp | 半導体基板の製造方法 |
| DE19840421C2 (de) | 1998-06-22 | 2000-05-31 | Fraunhofer Ges Forschung | Verfahren zur Fertigung von dünnen Substratschichten und eine dafür geeignete Substratanordnung |
| JP2000223682A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 基体の処理方法及び半導体基板の製造方法 |
| FR2795866B1 (fr) * | 1999-06-30 | 2001-08-17 | Commissariat Energie Atomique | Procede de realisation d'une membrane mince et structure a membrane ainsi obtenue |
| FR2795865B1 (fr) | 1999-06-30 | 2001-08-17 | Commissariat Energie Atomique | Procede de realisation d'un film mince utilisant une mise sous pression |
| US6352909B1 (en) * | 2000-01-06 | 2002-03-05 | Silicon Wafer Technologies, Inc. | Process for lift-off of a layer from a substrate |
| JP2002016239A (ja) | 2000-06-29 | 2002-01-18 | Canon Inc | 基板の処理方法及び製造方法 |
| JP2002134375A (ja) | 2000-10-25 | 2002-05-10 | Canon Inc | 半導体基体とその作製方法、および貼り合わせ基体の表面形状測定方法 |
| US6774010B2 (en) * | 2001-01-25 | 2004-08-10 | International Business Machines Corporation | Transferable device-containing layer for silicon-on-insulator applications |
| FR2823596B1 (fr) * | 2001-04-13 | 2004-08-20 | Commissariat Energie Atomique | Substrat ou structure demontable et procede de realisation |
| KR100557946B1 (ko) * | 2002-12-26 | 2006-03-10 | 주식회사 하이닉스반도체 | Bpsg막 형성 방법 |
-
2003
- 2003-09-30 FR FR0311450A patent/FR2860249B1/fr not_active Expired - Fee Related
-
2004
- 2004-09-23 US US10/574,120 patent/US8062564B2/en active Active
- 2004-09-23 CN CNB2004800338489A patent/CN100514560C/zh not_active Expired - Lifetime
- 2004-09-23 EP EP04787425A patent/EP1671361B1/de not_active Expired - Lifetime
- 2004-09-23 JP JP2006530396A patent/JP4932485B2/ja not_active Expired - Lifetime
- 2004-09-23 WO PCT/FR2004/002398 patent/WO2005034218A2/fr not_active Ceased
- 2004-09-23 AT AT04787425T patent/ATE358889T1/de not_active IP Right Cessation
- 2004-09-23 DE DE602004005731T patent/DE602004005731T2/de not_active Expired - Lifetime
- 2004-09-23 KR KR1020067008261A patent/KR101044503B1/ko not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007507872A (ja) | 2007-03-29 |
| KR101044503B1 (ko) | 2011-06-27 |
| US20080038564A1 (en) | 2008-02-14 |
| FR2860249A1 (fr) | 2005-04-01 |
| CN100514560C (zh) | 2009-07-15 |
| DE602004005731T2 (de) | 2007-12-27 |
| WO2005034218A2 (fr) | 2005-04-14 |
| US8062564B2 (en) | 2011-11-22 |
| FR2860249B1 (fr) | 2005-12-09 |
| EP1671361B1 (de) | 2007-04-04 |
| EP1671361A2 (de) | 2006-06-21 |
| CN1883031A (zh) | 2006-12-20 |
| KR20060117925A (ko) | 2006-11-17 |
| JP4932485B2 (ja) | 2012-05-16 |
| DE602004005731D1 (de) | 2007-05-16 |
| WO2005034218A3 (fr) | 2005-07-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |