ATE528654T1 - Schaltkreise zur verhinderung von spitzenleistungsproblemen während des scan-shift - Google Patents

Schaltkreise zur verhinderung von spitzenleistungsproblemen während des scan-shift

Info

Publication number
ATE528654T1
ATE528654T1 AT08705457T AT08705457T ATE528654T1 AT E528654 T1 ATE528654 T1 AT E528654T1 AT 08705457 T AT08705457 T AT 08705457T AT 08705457 T AT08705457 T AT 08705457T AT E528654 T1 ATE528654 T1 AT E528654T1
Authority
AT
Austria
Prior art keywords
during
circuits
periods
peak power
test clock
Prior art date
Application number
AT08705457T
Other languages
English (en)
Inventor
Chinsong Sul
Heon Kim
Original Assignee
Silicon Image Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Image Inc filed Critical Silicon Image Inc
Application granted granted Critical
Publication of ATE528654T1 publication Critical patent/ATE528654T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT08705457T 2007-03-08 2008-01-02 Schaltkreise zur verhinderung von spitzenleistungsproblemen während des scan-shift ATE528654T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/683,608 US7831877B2 (en) 2007-03-08 2007-03-08 Circuitry to prevent peak power problems during scan shift
PCT/US2008/000046 WO2008108902A1 (en) 2007-03-08 2008-01-02 Circuitry to prevent peak power problems during scan shift

Publications (1)

Publication Number Publication Date
ATE528654T1 true ATE528654T1 (de) 2011-10-15

Family

ID=39313485

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08705457T ATE528654T1 (de) 2007-03-08 2008-01-02 Schaltkreise zur verhinderung von spitzenleistungsproblemen während des scan-shift

Country Status (8)

Country Link
US (1) US7831877B2 (de)
EP (1) EP2122378B1 (de)
JP (2) JP5729906B2 (de)
KR (1) KR101421479B1 (de)
CN (1) CN101627314B (de)
AT (1) ATE528654T1 (de)
TW (1) TWI361283B (de)
WO (1) WO2008108902A1 (de)

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CN105807206B (zh) * 2016-03-11 2018-08-07 福州瑞芯微电子股份有限公司 一种芯片测试时钟电路及其测试方法
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TWI760400B (zh) * 2017-12-15 2022-04-11 英業達股份有限公司 以不同掃描鏈測試差分線路之系統及其方法
US10847211B2 (en) * 2018-04-18 2020-11-24 Arm Limited Latch circuitry for memory applications
KR102681969B1 (ko) * 2019-01-10 2024-07-08 삼성전자주식회사 논리 회로의 at-speed 테스트를 위한 시스템-온-칩 및 그것의 동작 방법
US11073557B2 (en) * 2019-05-08 2021-07-27 Texas Instruments Incorporated Phase controlled codec block scan of a partitioned circuit device
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CN112217498B (zh) * 2020-09-24 2023-04-14 联暻半导体(山东)有限公司 一种多位脉冲锁存器电路
CN112290932B (zh) * 2020-09-30 2022-09-06 上海兆芯集成电路有限公司 电路及其测试电路
CN114660445A (zh) 2020-12-23 2022-06-24 恩智浦美国有限公司 具有嵌入式存储器模块的集成电路
EP4043894B1 (de) * 2021-02-16 2023-09-13 STMicroelectronics S.r.l. Abtastkettenschaltung und entsprechendes verfahren
US11835991B2 (en) 2021-03-22 2023-12-05 Stmicroelectronics International N.V. Self-test controller, and associated method
US11604221B1 (en) * 2021-12-30 2023-03-14 Texas Instruments Incorporated Clock shaper circuit for transition fault testing
US12300338B2 (en) 2022-06-14 2025-05-13 Arm Limited Configurable scan chain architecture for multi-port memory
CN115425952B (zh) * 2022-09-06 2025-09-26 厦门紫光展锐科技有限公司 保持时间检测传感器、方法、芯片、芯片模组及电子设备
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Also Published As

Publication number Publication date
CN101627314B (zh) 2012-10-03
JP5729906B2 (ja) 2015-06-03
TWI361283B (en) 2012-04-01
KR20090126295A (ko) 2009-12-08
US20080222471A1 (en) 2008-09-11
WO2008108902A1 (en) 2008-09-12
EP2122378B1 (de) 2011-10-12
CN101627314A (zh) 2010-01-13
US7831877B2 (en) 2010-11-09
TW200842382A (en) 2008-11-01
KR101421479B1 (ko) 2014-07-22
JP2014102254A (ja) 2014-06-05
EP2122378A1 (de) 2009-11-25
JP2010520480A (ja) 2010-06-10

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