ATE546835T1 - Verfahren zur herstellung eines leiterrahmens - Google Patents

Verfahren zur herstellung eines leiterrahmens

Info

Publication number
ATE546835T1
ATE546835T1 AT02743870T AT02743870T ATE546835T1 AT E546835 T1 ATE546835 T1 AT E546835T1 AT 02743870 T AT02743870 T AT 02743870T AT 02743870 T AT02743870 T AT 02743870T AT E546835 T1 ATE546835 T1 AT E546835T1
Authority
AT
Austria
Prior art keywords
producing
conductor frame
plated
mounting surface
palladium
Prior art date
Application number
AT02743870T
Other languages
English (en)
Inventor
Kazunori Iitani
Youichirou Hamada
Original Assignee
Sumitomo Metal Mining Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001207316A external-priority patent/JP4852802B2/ja
Application filed by Sumitomo Metal Mining Co filed Critical Sumitomo Metal Mining Co
Application granted granted Critical
Publication of ATE546835T1 publication Critical patent/ATE546835T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/042—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H10W70/457—Materials of metallic layers on leadframes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • ing And Chemical Polishing (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
AT02743870T 2001-07-09 2002-07-09 Verfahren zur herstellung eines leiterrahmens ATE546835T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001207316A JP4852802B2 (ja) 2001-06-19 2001-07-09 リードフレーム
PCT/JP2002/006933 WO2003007373A1 (en) 2001-07-09 2002-07-09 Lead frame and its manufacturing method

Publications (1)

Publication Number Publication Date
ATE546835T1 true ATE546835T1 (de) 2012-03-15

Family

ID=19043321

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02743870T ATE546835T1 (de) 2001-07-09 2002-07-09 Verfahren zur herstellung eines leiterrahmens

Country Status (8)

Country Link
US (3) US7235868B2 (de)
EP (2) EP1406300B1 (de)
KR (2) KR101021600B1 (de)
CN (1) CN1317762C (de)
AT (1) ATE546835T1 (de)
ES (1) ES2383874T3 (de)
TW (1) TWI264099B (de)
WO (1) WO2003007373A1 (de)

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US8375577B2 (en) * 2008-06-04 2013-02-19 National Semiconductor Corporation Method of making foil based semiconductor package
US20100044850A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
JP5629969B2 (ja) 2008-09-29 2014-11-26 凸版印刷株式会社 リードフレーム型基板の製造方法と半導体装置の製造方法
JP4670931B2 (ja) * 2008-09-29 2011-04-13 住友金属鉱山株式会社 リードフレーム
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US8124447B2 (en) * 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US20110163430A1 (en) * 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof
CN102324414B (zh) * 2011-09-13 2013-06-26 江苏长电科技股份有限公司 有基岛预填塑封料先镀后刻引线框结构及其生产方法
CN102403282B (zh) * 2011-11-22 2013-08-28 江苏长电科技股份有限公司 有基岛四面无引脚封装结构及其制造方法
CN102661829A (zh) * 2012-04-28 2012-09-12 无锡永阳电子科技有限公司 So8塑料封装传感器
CN103456645B (zh) * 2013-08-06 2016-06-01 江阴芯智联电子科技有限公司 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法
CN103413766B (zh) * 2013-08-06 2016-08-10 江阴芯智联电子科技有限公司 先蚀后封芯片正装三维系统级金属线路板结构及工艺方法
CN103400771B (zh) * 2013-08-06 2016-06-29 江阴芯智联电子科技有限公司 先蚀后封芯片倒装三维系统级金属线路板结构及工艺方法
US10141197B2 (en) * 2016-03-30 2018-11-27 Stmicroelectronics S.R.L. Thermosonically bonded connection for flip chip packages
JP6777365B2 (ja) * 2016-12-09 2020-10-28 大口マテリアル株式会社 リードフレーム
CN113838761A (zh) * 2021-11-24 2021-12-24 新恒汇电子股份有限公司 物联网工业级卡的制备方法

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Also Published As

Publication number Publication date
EP1406300A1 (de) 2004-04-07
KR20030060885A (ko) 2003-07-16
US7521295B2 (en) 2009-04-21
US7235868B2 (en) 2007-06-26
CN1317762C (zh) 2007-05-23
US20050153482A1 (en) 2005-07-14
US20040169261A1 (en) 2004-09-02
US20070141756A1 (en) 2007-06-21
EP1406300A4 (de) 2007-11-21
ES2383874T3 (es) 2012-06-27
KR101021600B1 (ko) 2011-03-17
CN1526167A (zh) 2004-09-01
EP1406300B1 (de) 2012-02-22
EP2312630A1 (de) 2011-04-20
HK1069010A1 (en) 2005-05-06
KR100908891B1 (ko) 2009-07-23
KR20090009995A (ko) 2009-01-23
TWI264099B (en) 2006-10-11
WO2003007373A1 (en) 2003-01-23

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