EP0645687A2 - Circuit de génération d'une tension de référence - Google Patents

Circuit de génération d'une tension de référence Download PDF

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Publication number
EP0645687A2
EP0645687A2 EP94114599A EP94114599A EP0645687A2 EP 0645687 A2 EP0645687 A2 EP 0645687A2 EP 94114599 A EP94114599 A EP 94114599A EP 94114599 A EP94114599 A EP 94114599A EP 0645687 A2 EP0645687 A2 EP 0645687A2
Authority
EP
European Patent Office
Prior art keywords
node
potential
resistor
reference voltage
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94114599A
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German (de)
English (en)
Inventor
Noriaki C/O Intell.Pty.Div. Dobashi
Shinobu C/O Intell.Pty.Div. Shioda
Kanji C/O Intell.Pty.Div. Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0645687A2 publication Critical patent/EP0645687A2/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the present invention relates to a reference voltage generation circuit incorporated into a semiconductor integrated circuit and, in particular, to a reference voltage generation circuit whose circuit operation is not affected by the characteristic of elements, intrusion of noise.
  • a reference voltage generation circuit incorporated into a semiconductor integrated circuit is shown in U.S. Patent No. 4,263,519 issued to Schade, Jr.
  • the reference voltage generation circuit includes two NPN type bipolar transistors, three resistors for determining a reference voltage level, differential-input amplifier and two resistors for starting.
  • different emitter currents flow through the two NPN type bipolar transistors and, due to the emitter currents of these transistors, voltage drops occur across the two resistors one connected between the non-inverting input terminal of the differential-input amplifier and a ground potential node and one connected between the inverting input terminal of the differential-input amplifier and the ground potential node.
  • Both the drop voltages are supplied to the differential-input amplifier and a voltage on the output terminal of the differential-input amplifier is applied to the bases of the transistors to provide a negative feedback.
  • an input offset voltage occurs in the differential-input amplifier due to some causes, such as a variation in the characteristic of elements in manufacture.
  • a potential on the output terminal stays at a ground level without any normal operation at a time of turning a power supply ON.
  • a reference voltage of a normal level sometimes skips to a ground level due to the intrusion of noise, and it is still possible to regain a normal operation with the use of such two resistors for starting.
  • a reference voltage generation circuit comprising: a first node for receiving a first potential; a second node for receiving a second potential different in level from the first potential; a first bipolar transistor having a collector connected to the first node, an emitter and a base; a second bipolar transistor having a collector connected to the first node, an emitter, and a base connected to that of the first bipolar transistor to provide a common base connection node, and having the same polarity as that of the first bipolar transistor; a first resistor having one end connected to the emitter of the first bipolar transistor and the other end; a second resistor having one end connected to the other end of the first resistor and the other end connected to the second node; a third resistor having one end connected to the emitter of the second bipolar transistor and the other end connected to the second node; a differential-input amplifier having a non-inverting input terminal connected to a series connection node between the first resistor and the second resistor, an in
  • a reference voltage generation circuit includes, as shown in FIG. 1, two NPN type bipolar transistors 11, 12, three resistors 13, 14, 15, differential-input amplifier 16 and starting circuit 30.
  • the collector of one transistor 11 is connected to a node 17 supplied with a positive power supply potential V DD .
  • One end of the resistor 13 is connected to the emitter of the transistor 11.
  • One end of the resistor 14 is connected to the other end of the resistor 13.
  • the other end of the resistor 14 is connected to a node 18 supplied with a ground potential V SS .
  • the collector of the other transistor 12 is connected to the node 17.
  • the base of the transistor 12 is connected to that of the transistor 11.
  • One end of the resistor 15 is connected to the emitter of the transistor 12.
  • the other end of the resistor 15 is connected to the node 18.
  • the differential-input amplifier 16 has an inverting input terminal (-), non-inverting input terminal (+) and output terminal.
  • the non-inverting input terminal (+) of the amplifier 16 is connected to a connection node 19 between the resistors 13 and 14 and the inverting input terminal (-) of the amplifier 16 is connected to a connection node 20 between the emitter of the transistor 12 and the resistor 15.
  • the starting circuit 30 delivers an output close to a power supply potential V DD level to the node 19.
  • a series circuit of the two resistors 13 and 14 is connected between the emitter of the transistor 11 and the node 18 of a ground potential and the resistor 15 is connected between the emitter of the transistor 12 and the node 18 of the ground potential.
  • the respective transistors 11 and 12 have different emitter current levels. Voltage drops occur one across the resistor 14 and one across the resistor 15 due to the emitter currents of the transistors 11 and 12.
  • the corresponding drop voltages are supplied to the non-inverting input terminal (+) and inverting input terminal (-) of the differential-input amplifier 16.
  • the potential on the output terminal of the differential-input amplifier 16 is supplied to the respective bases of the transistors 11 and 12 to provide a negative feedback.
  • a reference voltage V ref is obtained from the output terminal of the differential-input amplifier 16.
  • the node 19 Since, in reality, the starting circuit 30 is present, the node 19 is placed, instead of staying at the ground potential as set out above, at a predetermined potential close to a power supply potential V DD due to the operation of the starting circuit 30 after the power supply is rendered ON. At this time, current flows through the resistor 14 and a voltage drop occurs across the resistor 14, thus leading a rise in potential of the node 19. Since the potential of the node 19 is increased relative to the potential of the node 20 to an extent that the input offset voltage of the differential-input amplifier 16 can be disregarded, the differential-input amplifier 16 performs a comparator operation and the output potential of the output terminal is raised.
  • the base ⁇ emitter voltage V BE is applied to the transistors 11 and 12 and emitter currents start to flow through the transistors 11 and 12.
  • V ref a reference voltage
  • the output potential of the starting circuit 30 is supplied to the non-inverting input terminal of the differential-input amplifier 16, not to the bases of the transistors 11 and 12. It is only necessary that a potential greater than the input offset voltage of the differential-input amplifier 16 be generated on the starting circuit 30. It is therefore not necessary to increase the current drive capability of the starting circuit to such an extent as required in the prior art circuit.
  • a starting circuit 30 as shown in FIG. 2 comprises a constant current source 31, resistor 32 and NPN type bipolar transistor 33.
  • One end of the constant current source 31 is connected to the node 17 of a power supply potential V DD and the transistor 32 is connected between the other end of the constant current source 31 and a ground potential V SS .
  • the collector of the transistor 33 is connected to the node 17, the base of the transistor 33 is connected to a node 34 of a series circuit of the constant current source 31 and resistor 32 and the emitter of the transistor 33 is connected to the node 19.
  • a predetermined bias potential greater than the base ⁇ emitter voltage V BE of the transistor 33 is placed with respect to the emitter potential of the transistor 33 after the power supply is turned ON. This state is achieved by setting the value of the resistor 32 and current value of the constant current source 31. Even if the potential of the node 19 stays at a ground potential after the power supply is turned ON, the transistor 33 is turned ON through the supplying of the bias potential to the base of the transistor 33. As a result, current flows in the resistor 14 via the transistor 33 and a voltage drop occurs across the resistor 14. Thereafter, a differential-input amplifier 16 performs a comparator operation and a reference voltage V ref is delivered as an output signal from an output terminal.
  • a starting circuit 30 as shown in FIG. 3 is of such a type that a resistor 35 is used in place of the constant current source 31 in the circuit shown in FIG. 2.
  • a bias potential level emerging of a node 34 is set in accordance with a ratio of two resistors 35, 32 and power supply (V DD ) level.
  • a starting circuit 30 as shown in FIG. 4 is constructed of a capacitance 36 connected between the node 17 of a power supply potential V DD and the node 19.
  • a potential of the node 19 is raised above the ground potential through the capacitive coupling made by the capacitance 36. Thereafter, the potential of the node 19 is increased to an extent that the offset voltage of a differential-input amplifier 16 can be disregarded.
  • the differential-input amplifier 16 performs a comparator operation and its output voltage is raised.
  • a base ⁇ emitter voltage V BE is applied to transistors 11 and 12, thus allowing current to start flowing in the transistors 11 and 12.
  • the transistors 11, 12 and differential-input amplifier 16 allow a negative feedback operation and, finally, a reference voltage V ref is obtained as a desired predetermined level.
  • a starting circuit 30 as shown in FIG. 5 is of such a type that an N channel type MOS transistor 37 is employed in place of an NPN type bipolar transistor 33 in the circuit of FIG. 2. That is, the drain of the MOS transistor 37 is connected to the node 17 of a power supply potential V DD , the source of the MOS transistor 37 to the node 19 and the gate of the MOS transistor 37 to the node 34.
  • the base ⁇ emitter voltage V BE of the NPN type bipolar transistor 33 corresponds to the threshold voltage of the N-channel type MOS transistor 37. That is, after the power supply is turned ON, the potential of the node 34 is set to a predetermined bias potential relative to a source potential of the MOS transistor 37, the predetermined bias voltage being above the threshold voltage. This is realized by setting the value of a resistor 32 and current level of a constant current source 31. Even in the case where a potential of the node 19 stays at a ground potential after a power supply is turned ON, the MOS transistor 37 is turned ON through the application of the bias potential to the gate of the MOS transistor. Current flows in the resistor 14 through the MOS transistor 37 and a voltage drop occurs across the resistor 14. Thereafter, the differential-input amplifier 16 performs a comparator operation and a reference voltage V ref emerges as an output from an output terminal.
  • the potential of the node 19 goes higher than a ground potential and no gate ⁇ source potential above the threshold voltage emerges on the MOS transistor 37. Thereafter, the MOS transistor 37 is cut off and no current flows in the MOS transistor 37 so that no influence is exerted on the current in a transistor 11.
  • a starting circuit 30 as shown in FIG. 6 is of such a type that a diode 38 is used in place of the NPN type bipolar transistor 33 in the circuit shown in FIG. 2.
  • the base ⁇ emitter voltage V BE of the NPN type bipolar transistor 33 corresponds to a forward drop voltage V F of the diode 38. That is, after a power supply is turned ON, a potential of the mode 34 is set to a predetermined bias potential with respect to the cathode potential of the diode 38, the predetermined bias potential being above a forward drop voltage V F . That is realized by setting the values of resistors 32 and 35.
  • the diode 38 is turned ON through the application of the bias potential to the anode and current flows in the resistor 14 through the diode 38 and a voltage drop occurs across the resistor 14. Thereafter, the differential-input amplifier 16 performs a comparator operation and a reference voltage V ref is delivered as an output voltage from the output terminal.
  • the circuit of the second embodiment is different from that of the first embodiment in that, in the second embodiment, the output potential of the starting circuit 30 is applied to a connection node 21 between the emitter of the transistor 11 and the resistor 13 instead of being applied to the node 19.
  • the potential of the node 19 is raised to a level close to the power supply potential V DD by applying the output potential of the starting circuit 30 to the node 19.
  • the same effect can be obtained by applying the output potential of the starting circuit 30 to the node 21, not to the node 19.
  • the output voltage of the starting circuit 30 is divided by two resistors 13 and 14 and, through the node 19, applied to the non-inverting input terminal of the differential-input amplifier 16. Therefore, since the potential of the node 19 is lower than that in the embodiment shown in FIG. 1, the potential of the node 19 can be raised up to a level adequately close to a power supply potential V DD .
  • a starting circuit 30 shown in FIG. 8 comprises a constant current source 31, resistor 32 and NPN type bipolar transistor 33.
  • a starting circuit 30 shown in FIG. 9 uses a resistor 35 in place of the constant current source 31 in the circuit shown in FIG. 8.
  • a starting circuit 30 shown in FIG. 10 is of such a type that it comprises a capacitance 36 connected between the node 17 of a power supply potential V DD and the node 21.
  • a starting circuit 30 shown in FIG. 11 uses an N channel type MOS transistor 37 in place of the NPN type bipolar transistor 33 in the circuit shown in FIG. 8.
  • a starting circuit 30 shown in FIG. 12 uses a diode 38 in place of the NPN type bipolar transistor 33 in the circuit shown in FIG. 9.
  • a reference voltage generating circuit according to a third embodiment of the present invention shown in FIG. 13 uses PNP type bipolar transistors 22, 23 instead of the NPN type bipolar transistors 11, 12 in the embodiment shown in FIG. 1 and the node 17 of a power supply potential V DD and the node 18 of a ground potential V SS are connected in a reversed relation to those in the first embodiment shown in FIG. 1.
  • a starting circuit 40 in which, in the case where, after the turning ON of a power supply, a reference voltage V ref obtained as the output terminal of a differential-input amplifier 16 stays at a power supply potential due to some reasons, such as the input offset of the differential-input amplifier 16 and intrusion of noise, a starting circuit 40 delivers a predetermined potential as an output close to a ground potential V SS to the connection node 19 between resistors 13 and 14.
  • V ref V DD - ⁇ V BE + (R2/R1)V T ln(R2/R3) ⁇ 2 is obtained from the output terminal of the differential-input amplifier 16.
  • the node 19 which might otherwise stay at the power supply potential as set out above is set to a potential close to a ground potential V SS through the operation of the starting circuit 40 after the turning ON of the power supply.
  • V SS ground potential
  • the potential drop of the node 19 is made greater to an extent that the offset voltage of the differential-input amplifier 16 can be disregarded.
  • the differential-input amplifier 16 performs a comparator operation and an output potential emerges, as a dropped one, from the output terminal.
  • the base ⁇ emitter voltage V BE is applied to the transistors 22 and 23 and emitter current starts flowing through the transistors 22 and 23.
  • the negative feedback path comprising the transistors 22, 23 and differential-input amplifier 16, it is possible to obtain a reference voltage V ref of a desired level given by Equation 2.
  • the starting circuit 40 as shown in FIG. 14 comprises a constant current source 41, resistor 42 and PNP type bipolar transistor 43.
  • One end of the constant current source 41 is connected to the node 18 of a ground potential V SS and the resistor 42 is connected between the other end of the constant current source 41 and the node 17 of a power supply potential V DD .
  • the collector of the transistor 43 is connected to the node 18, the emitter of the transistor 43 to the node 19 and the base of the transistor 43 to a connection node 44 between the constant current source 41 and the resistor 42.
  • the potential of the node 44 is set to a predetermined bias potential lower by over the base ⁇ emitter voltage V BE level than the emitter potential of the transistor 43. This is realized by setting the value of the resistor 42 and current value of the constant current source 41. Even in the case where the potential of the node 19 stays at the power supply potential after the turning ON of the power supply, the transistor 43 is turned ON through the application of a bias potential of the node 44 to the base of the transistor and, through the transistor 43, current flows through the resistor 14 to allow a voltage drop to occur across the resistor 14. Thereafter, a differential-input amplifier 16 performs a comparator operation and a reference voltage V ref emerges as an output voltage from the output terminal.
  • a starting circuit 40 as shown in FIG. 15 uses a resistor 45 in place of the constant current source 41 in the circuit shown in FIG. 14.
  • a bias potential on the node 44 is set in accordance with a ratio of two resistors 45, 42 and level of a power supply potential V DD .
  • a starting circuit 40 as shown in FIG. 16 comprises a capacitance 46 connected between the node 18 of a ground potential V SS and the node 19.
  • a potential of the node 19 is made lower than a power supply potential through a capacitive coupling made by a capacitance 46.
  • the potential of the node 19 is lowered, as in the above case, relative to the potential of the node 20 to an extent that an offset voltage of a differential-input amplifier 16 can be disregarded.
  • the differential-input amplifier 16 performs a comparator operation and the output voltage of the differential-input amplifier 16 is dropped.
  • the base ⁇ emitter voltage V BE is applied to transistors 22 and 23, thus allowing current to start flowing in the transistors 22 and 23.
  • a negative feedback operation is made through the transistors 22, 23 and differential-input amplifier 16. It is, therefore, possible to finally obtain a reference voltage V ref of a desired given level.
  • a starting circuit 40 as shown in FIG. 17 uses a P channel type MOS transistor 47 in place of the PNP type bipolar transistor 43 in the circuit shown in FIG. 14.
  • the drain of the MOS transistor 47 is connected to the node 18, the source of the transistor 47 to the node 19 and the gate of the transistor to the node 44.
  • the base ⁇ emitter voltage V BE of the bipolar transistor 43 corresponds to the threshold voltage of the MOS transistor 47.
  • a starting circuit 40 as shown in FIG. 18 uses a diode 48 in place of the PNP type bipolar transistor 43 in the circuit shown in FIG. 14.
  • the base ⁇ emitter voltage V BE of the bipolar transistor 43 corresponds to a forward drop voltage V F of the diode 48.
  • a reference voltage generation circuit according to a fourth embodiment of the present invention as shown in FIG. 19 comprises, as in the third embodiment of FIG. 13, two PNP type bipolar transistors 22, 23, three resistors 13, 14, 15, differential-input amplifier 16 and starting circuit 40.
  • the embodiment of FIG. 19 is different from that of FIG. 13 in that an output potential of its starting circuit 40 is applied to the node 24 between the emitter of the transistor 22 and the resistor 13 instead of being connected to the node 19.
  • the potential of the node 19 is lowered to a level close to a ground potential V SS by connecting the output potential of the starting circuit 40 directly to the node 19.
  • the same effect as in the third embodiment is obtained by applying the output potential of the starting circuit 40 to the connection node 24 between the emitter of the transistor 22 and the resistor 13 instead of being applied to the node 19.
  • the output potential of the starting circuit 40 being divided by the resistors 13 and 14, is supplied to a non-inverting input terminal of the differential-input amplifier 16.
  • the potential of the node 19 is made higher than that in the embodiment of FIG. 13, but the potential of the node 19 can be lowered enough close to a ground potential V SS .
  • a starting circuit 40 of FIG. 20 comprises a constant current source 41, resistor 42 and PNP type bipolar transistor 43.
  • a starting circuit 40 of FIG. 21 uses a resistor 45 in place of the constant current source 41 in the circuit of FIG. 20.
  • a starting circuit 40 of FIG. 22 comprises a capacitance 46 connected between the node 18 of a ground potential V SS and the node 24.
  • a starting circuit 40 of FIG. 23 uses a P channel type MOS transistor 47 in place of the PNP type bipolar transistor 43 in the circuit shown in FIG. 20.
  • a starting circuit 40 of FIG. 24 uses a diode 48 in place of the PNP type bipolar transistor 43 in the circuit shown in FIG. 21.
  • a reference voltage generation circuit which can stably operate at all times without being adversely affected even if there is a variation in the characteristic of elements, intrusion of noise.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
EP94114599A 1993-09-29 1994-09-16 Circuit de génération d'une tension de référence Withdrawn EP0645687A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP242507/93 1993-09-29
JP24250793A JP3313475B2 (ja) 1993-09-29 1993-09-29 基準電圧発生回路

Publications (1)

Publication Number Publication Date
EP0645687A2 true EP0645687A2 (fr) 1995-03-29

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EP94114599A Withdrawn EP0645687A2 (fr) 1993-09-29 1994-09-16 Circuit de génération d'une tension de référence

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EP (1) EP0645687A2 (fr)
JP (1) JP3313475B2 (fr)
KR (1) KR950010338A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006031549A1 (de) * 2006-07-07 2008-01-31 Infineon Technologies Ag Bandabstandsreferenzschaltung mit einer Hochfahrschaltung und Verfahren zum Hochfahren einer Bandabstandsreferenzschaltung

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006031549A1 (de) * 2006-07-07 2008-01-31 Infineon Technologies Ag Bandabstandsreferenzschaltung mit einer Hochfahrschaltung und Verfahren zum Hochfahren einer Bandabstandsreferenzschaltung
US7911195B2 (en) 2006-07-07 2011-03-22 Infineon Technologies Ag Electronic circuits and methods for starting up a bandgap reference circuit
DE102006031549B4 (de) * 2006-07-07 2016-08-04 Infineon Technologies Ag Verfahren zum Betreiben einer Hochfahrschaltung für eine Bandabstandsreferenzschaltung, Verfahren zum Unterstützen des Hochfahrens einer Bandabstandsreferenzschaltung und elektronische Schaltung zur Durchführung der Verfahren

Also Published As

Publication number Publication date
KR950010338A (ko) 1995-04-28
JPH0798614A (ja) 1995-04-11
JP3313475B2 (ja) 2002-08-12

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