Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/351—Substrate regions of field-effect devices
  • H10D62/357—Substrate regions of field-effect devices of FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/351—Substrate regions of field-effect devices
  • H10D62/357—Substrate regions of field-effect devices of FETs
  • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
  • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

• the present invention relates generally to the techniques for producing high electron mobility transistors (or HEMT transistor, the English “High Electron Mobility Transistor”). It relates more particularly to a hetero structure from which such a transistor can be made.
• the invention finds applications, in particular in the field of power electronic components used, for example, in devices for producing, converting and / or managing renewable energies such as wind or solar energy, but also in transport with low ecological impact.
• renewable energy sources such as wind and solar energy
• means of transport with low environmental impact such as the tramway, the train or the electric car
• suitable electronic power components and more, especially of power switches.
• improvements to semiconductor type components in the form of integrated circuits, such as power transistors relate to the intrinsic characteristics of these components to increase their operating voltage and / or their maximum switching frequency. They also aim to offer total integration solutions allowing mass manufacturing to reduce production costs.
• Si silicon-based power components
• MOS metal oxide semiconductor
• IGBT insulated gate bipolar transistor
• SiC Silicon Carbide
• GaN Gallium Nitride
• FIG. 1 is shown an example of heterojunction electronic structure used in a HEMT transistor.
• This heterojunction electronic structure comprises several layers based on GaN each having intrinsic characteristics under control, and stacked one above the other, with:
• buffer layer made of a material M1 characterized by its bandgap or "gap"Eg1; and, a second layer 5, called barrier layer, coming over the first layer 3 and composed of a material M2 characterized by its bandgap width or "gap" Eg2, where Eg1 is smaller than Eg2.
• MOS-HEMT transistor structure is proposed in the IEEE publication of 2008, "Enhanced device performance of AIGaN / GaN HEMTs using thermal oxidation of electron-beam deposited aluminum for gas oxide" by C. Hongwei et al.
• This publication shows the improved performance of a conventional HEMT transistor structure that can be achieved by adding an oxidation layer at the gate electrode.
• the MOS-HEMT structure thus obtained has lower leakage currents and a larger drain current range than a conventional HEMT structure with, however, the need to have a threshold voltage of less than zero volts to set the transistor in a blocked state.
• a Fluorine doped zone is inserted into the barrier layer of the HEMT transistor structure AIGaN / GaN and this latter is placed below the gate electrode, the Fluor ion doses being determined to have an sufficient offset of the voltage Vgs of the transistor.
• N Devices and Circuits' further proposes a further development of the method of manufacturing a HEMT transistor structure.
• a Fluorine plasma treatment method is used on the barrier layer of the hetero-structure. This method makes it possible, with a relatively simple process (use of a fluorine plasma), to modify the intrinsic characteristics of the hetero-structure in order to obtain an "normally OFF" transistor.
• the patent application US2013 / 0256685 entitled “Compound semiconductor device and method for manufacturing the same” proposes a structure based on HEMT transistor in which a two-dimensional gas of electrons is generated, and an electrode is formed on the transistor-based structure.
• the structure further includes a P-type semiconductor layer below an area where the two-dimensional electron gas is generated.
• the P-type semiconductor layer has a portion containing a larger amount of ionized acceptors than other portions of the P-type semiconductor layer.
• the object of the invention is to overcome the disadvantages of the aforementioned prior art, and more particularly to allow the realization of an HEMT transistor with a low leakage current at the gate, a high switching speed and a higher threshold voltage. at 0 V to ensure "normally OFF" functionality.
• a first aspect of the invention proposes a heterojunction structure, in particular for a high electron mobility transistor (HEMT) comprising: a planar substrate,
• a first non-intentionally doped buffer layer is arranged on the substrate
• a third non-intentionally doped buffer layer disposed on the second buffer layer and having a predetermined thickness in a direction orthogonal to the substrate plane
• barrier layer disposed on the intermediate layer disposed, said barrier layer being made of a column III nitride based wide bandgap semiconductor material Eg2,
• the second buffer layer has substantially constant P + type doping over all or part of its thickness
• the third buffer layer comprises a first region which is unintentionally doped throughout its thickness, as well as at least one second region adjacent to said first region and which is doped with N + type doping.
• the second region adjacent to the first region of the third buffer layer has a constant doping throughout the thickness of said third buffer layer thus controlling the formation of 2DEG bidimensional gas.
• the second region adjacent to the first region of the third buffer layer has a Gaussian type doping according to the thickness of said third buffer layer.
• a distance in a direction orthogonal to the plane of the substrate, between the second buffer layer and the interface between the intermediate layer and the barrier layer is less than 20 nm, which makes it possible to control and to locally elevate the Fermi level and the conduction band of the heterojunction.
• the nitride semiconductor material of the column III of which are formed the first buffer layer, the second buffer layer, the third buffer layer, the layer disposed on the third buffer layer and the layer barrier comprises GaN.
• N + type doping may be used to dopate the region adjacent to the first region of said third buffer layer and the dopant is preferably silicon.
• a transition layer is interposed between the substrate and the first buffer layer.
• a second aspect of the invention relates to a HEMT type transistor made from a hetero-structure as described above.
• the transistor comprises a surface gate electrode determined in a first plane parallel to the plane of the substrate, a drain electrode and a source electrode disposed in a second plane above the barrier layer of the heterojunction structure.
• the first and second shots can be confused or staggered.
• the first region of the third buffer layer of the heterojunctional structure is disposed beneath the gate electrode, and has a surface in a plane parallel to the plane of the substrate that is less than or equal to said surface of the gate electrode.
• such a transistor may have an oxide-based insulating layer on the barrier layer below the gate electrode for controlling leakage currents.
• the insulating layer has a surface in a plane parallel to the plane of the substrate identical to the surface of the gate electrode.
• a semiconductor product comprising at least one transistor according to the second aspect.
• This may be, for example, a power switch or any other power component such as a power voltage regulator, for example.
• the invention relates to a method of manufacturing such a hetero-structure which comprises:
• ⁇ depositing a second buffer layer on the first buffer layer having a thickness determined according to a direction orthogonal to the plane of the substrate and doping said second buffer layer being formed using dopant of the P + type throughout its thickness ;
• the intermediate layer and the barrier layer cover all of the buffer layers, and therefore the electrodes of the transistor mounted above will not be in direct contact with the P + doped layer.
• this manufacturing method is simple and requires few additional steps compared to the manufacture of a conventional hetero-structure, for example for the production of a conventional HEMT transistor.
• the successive deposits of the stack of layers are made without interruption of an epitaxial process.
• FIG. 2 is a sectional view of an example of stacking layers forming a heterojunction structure according to one embodiment of the invention
• Figures 3 to 14 are sectional views illustrating the main technological steps for the realization of the heterojunction structure of Figure 2;
• FIG. 15 is a sectional view of an HEMT transistor according to one embodiment
• Figure 16 is a top view and Figures 17 and 18 are side views showing the position of the gate electrode of the transistor relative to a first unintentionally doped region of an underlying buffer layer;
• FIG. 19 is a graph showing the threshold voltage and the current of the transistor of FIG. 15 as a function of its gate-source voltage
• FIG. 20 is a sectional view of an example HEMT transistor according to another embodiment. Detailed description of embodiments
• the invention will be more particularly described in a nonlimiting example of application to a heterojunction structure 2 for HEMT transistors.
• the heterojunction structure example 2 described below is based on nitrides of elements of column III of the periodic table of the elements, also called Mendeleev table. It relates more particularly to a heterojunction structure 2 based on nitrided materials to form an AIGaN / GaN type interface.
• the GaN is a semiconductor material with a forbidden bandwidth Eg1 smaller than a bandgap width Eg2 of the AIGaN material.
• a heterojunction structure that uses the properties of another type of semiconductor material for creating an interface between GaAIAs-type large gap material and a GaAs-type small gap material can be used. performed.
• FIG. 2 shows a first example of stack of buffer layers constituting structure 2 with heterojunction. It comprises in ascending order of stacking: a plane substrate 4,
• a first non-intentionally doped buffer layer 6 is arranged on the substrate 4,
• a second buffer layer 8 disposed on the first layer 6 and having a thickness determined according to a direction orthogonal to the substrate plane
• Non intentionally doped buffer layer disposed on the second buffer layer 8 and having a thickness determined according to a direction orthogonal to the substrate plane, an unintentionally doped intermediate layer 1 1 disposed on the third buffer layer 10 made of a wide-band semiconductor forbidden semiconductor material Eg1 of column III identical to that of the stack of buffer layers, - a barrier layer 12 arranged on the intermediate layer 11, said barrier layer 12 being made of a nitride-based broadband semiconductor material Eg2 of column III, in which:
• the second buffer layer 8 has a substantially constant P + type doping over all or part of its thickness
• the third buffer layer 10 comprises a first region 16 which is unintentionally doped throughout its thickness, and at least one second region 18 adjacent to said first region 16 and which is doped with N + type doping. It is noted that buffer layers 6, 8, 10, the intermediate layer
• the barrier layer 12 extend continuously in stacking over the entire surface of the structure; the second 8 covering continuously and entirely the first 6; the third 10 covering continuously and entirely the second 8; the intermediate layer 1 1 covering continuously and entirely the third 10, the barrier layer 12 continuously and completely covering the intermediate layer January 1.
• the P + type doping mentioned herein corresponds to a density of between 10 17 and 18 cm -3 , preferably between 10 18 and 19 cm -3 .
• first buffer layer 6 Depositing a first buffer layer 6 on the substrate 4, said semiconductor material which is made of said first buffer layer being unintentionally doped, ⁇ depositing a second buffer layer 8 of the first buffer layer 6 having a thickness determined according to a direction orthogonal to the plane of the substrate and doping said second buffer layer being formed with elements P type dopants on + all its thickness,
• barrier layer 12 of a nitride-based wide bandgap semiconductor material of column III depositing a barrier layer 12 of a nitride-based wide bandgap semiconductor material of column III on the layer 11.
• the performance of the heterojunction structure 2 having a stack of layers depends inter alia on the crystalline quality of the epitaxial material used.
• GaN is an epitaxial material which makes it possible to limit partial disagreements of mesh with the materials forming the hetero-structure. To do this, the GaN is obtained by crystallographic growth from the substrate 4.
• SiC silicon carbide
• Si silicon carbide
• substrates such as substrates based on GaAs, ZnO or so-called "free standing" substrates may also be used.
• silicon (Si) may also be used.
• the Si is a material that is commonly used for the manufacture of electronic components in general and HEMT transistors in particular. The massive and old use of Si in electronic components makes it a material whose intrinsic characteristics are very well controlled with above all a very low cost price despite a higher mesh size than SiC.
• the heterojunction structure 2 can be carried out on a substrate Si of crystalline orientation determined, for example that noted (1 1 1) in the literature. It may sometimes be necessary to deposit a transition layer 14 as illustrated in FIG. 3, more commonly known as a nucleation layer, in order to overcome any dislocation problems. This transition layer 14 can also reduce the risk of tearing between the layers. These tears are generally due to the difference in mechanical stresses internal to the interface between the layers. Thus, for example and as illustrated in Figure 3, the transition layer 14 may be disposed between the substrate 4 and the first buffer layer 6 of the stack of buffer layers.
• transition layers can be deposited between two layers.
• nucleation layers may be deposited, for example in several successive deposition operations, on another layer of nitride compounds by epitaxy.
• this makes it possible to improve and / or control the quality of the first buffer layer 6 in order to avoid, for example, tearing off or the creation of gaps that could generate uncontrolled leakage currents.
• the substrate Si may be of crystalline orientation other than (001) or even (100), and that, if necessary, intermediate layers may be used, as previously stated, in order to obtain a film of GaN in concordance with the specifications of the application. It should be noted that the substrates described above are mentioned here only by way of example and are not limiting of the invention.
• the growth of the various layers of structure 2 heterojunction can be achieved using microelectronics techniques, such as for example a technique by vapor phase epitaxy in reactors of HVPE type (English “Hybrid Vapor Phase Epitaxy "), From certain gaseous mixtures of type for example GaCl3 / NH3.
• HVPE Hydrophosphide
• This technique makes it possible, thanks to high growth rates, to obtain relatively large thicknesses and excellent qualities.
• the growth of the first buffer layer 6 of the stack of layers can be obtained by the MOCVD method, for example by using elements of column III, in particular by routing in a reaction chamber. It may be, for example, a mixture of dihydrogen as well as a chemical precursor.
• the GaN is thus formed on the surface of the transition layer 14 to form the first buffer layer 6.
• the first buffer layer 6 is unintentionally doped.
• a layer unintentionally doped GaN is also called UID-GaN (unintentionally doped), GaN-NID (from French). "GaN Not Intentionally Doped"), or i-GaN ("intrinsic GaN” or “intrinsic GaN”).
• the second buffer layer 8 (FIG. 5) is then deposited on the first buffer layer 6.
• the second buffer layer 8 is produced without the epitaxial process being interrupted, that is to say without the substrate 4 removed from the epitaxy chamber or undergo other technological steps.
• the quality of the interfaces between the different layers is substantially improved.
• the process time is decreased, which substantially reduces the production costs of the structure 2 to heterojunction.
• the growth process of the second buffer layer 8 by epitaxy relies substantially on the same method as that described in the preceding paragraphs for the first buffer layer 6.
• a P-type doping element is used during the growth process of the latter.
• the P-type doping element preferentially belongs to the elements of column II-A such as, for example, magnesium (Mg).
• Mg magnesium
• other dopants of this same column of the Mendeleev periodic table can also be used, such as for example Beryllium.
• the doses of doping elements during the growth process of the second buffer layer 8 can be modulated to obtain a layer with a determined doping corresponding to a precise specification of the application.
• the second buffer layer 8 has a minimum thickness of 400 nm in order to obtain threshold voltages shifted to positive values.
• the heterojunction structure 2 further comprises a third GaN buffer layer 10 as illustrated in FIG. 6.
• the material of this third buffer layer 10 as well as the intrinsic characteristics are preferentially identical to the characteristics of the first layer. buffer 6 of the stack of layers.
• the third buffer layer 10 is unintentionally doped UID-GaN. The method for obtaining this layer is identical to that presented above for producing the first buffer layer 6.
• the third buffer layer 10 also has a thickness of the order of 10 nm for shifting the threshold voltage of the HEMT to positive values. .
• the heterojunction structure 2 has a lower risk of tearing the films constituting the different layers.
• the cost of manufacturing such a heterojunction structure 2 is substantially reduced compared to the structures of the prior art.
• a first region 16 and at least one region adjacent to this region 16 such as adjacent regions 18 located on either side of the region 16 in the layer view of FIG. 7. It will be noted that, seen from above, the two regions 18 of FIG. 7 can be only one and even area 18 surrounding area 16.
• a masking or protective layer 20 which makes it possible to precisely delimit the first region 16.
• This mask 20 may be made for example with a photosensitive polymer allowing Using conventional photolithography techniques, to delimit the first region 16. This method of delimitation using a polymer is well known to those skilled in the art it will not be more detailed here.
• an ion implantation process is performed on the entire surface of the third buffer layer 10 which is not protected by the mask 20.
• an N-type dopant such as Si.
• Localized implantation or otherwise called localized doping of a GaN layer requires relatively high dopant energies. Indeed, to penetrate the dopants in depths of a few nm in the GaN layer, it is necessary to use energies of the order of a few tens or even hundreds of keV. Such energies are necessary because of a relatively high GaN atomic density compared for example with that of silicon. Ion implantation processes are now well known, controlled and therefore will not be presented here.
• an annealing is performed so that the doping species are positioned in substitutional sites (activation). Annealing is also used so that the GaN recrystallizes following the damage caused by the implantation.
• the annealing temperature is of the order of 1000 ° C.
• this implantation step makes it possible to cancel the influence of the presence of the second P-doped buffer layer 8 on the two-dimensional electron gas at the two regions 18.
• the N + type doping in the third buffer layer 10 is of Gaussian form as schematically illustrated in Figure 9a.
• an unintentionally doped intermediate layer 11 is then deposited on the third buffer layer 10.
• the material constituting the intermediate layer 11 may be formed of a wide bandgap semiconductor material Eg1 based on nitride column III identical to that of the stack of buffer layers.
• the intermediate layer 1 1 is unintentionally doped UID-GaN.
• the method for obtaining this layer is identical to that presented above for producing the first buffer layer 6.
• the intermediate layer 1 1 further has a thickness between 10 and 30 nm, preferably of the order of 10 nm to shift the voltage threshold of the HEMT to positive values.
• a barrier layer 12 is then deposited on the unintentionally doped intermediate layer 11.
• the material constituting the barrier layer 12 may be formed of a semiconductor material having a bandwidth Eg 2.
• this layer may be composed of AIGaN, such as AIGa (1-x) N, where x is the mole fraction and is between 0 and 1, with a thickness of the barrier layer 12 less than 1 ⁇ .
• the barrier layer 12 may be composed of several layers with respective controlled characteristics, such as, for example, a doped layer, called a donor layer providing electrons involved in the formation of two-dimensional gas. electron.
• the heterojunction structure 2 which has been presented above allows an improvement, for example, in controlling the threshold voltages of the HEMT transistors in order to obtain "normally OFF" transistors.
• such a structure makes it possible to obtain a transistor with improved reliability.
• the third buffer layer 10 is doped with an N-type dopant element during the growth process of the latter.
• the N-type doping element may be Si.
• the third buffer layer 10 is locally etched preferentially with the aid of, for example, a dry etching solution.
• the third N + doped buffer layer 10 is produced by a so-called "lift" method of deposition for defining the first region 16 without etching of the third buffer layer 10.
• the GaN-NID layer 10.1 is performed ( Figure 14).
• the first buffer layer 6, layer 1 1 and the first region 16 may have a slight N-doping (10 16 to 10 17 cm “3) much lower than the N + doping (October 19 to October 20 cm" 3) of the region 18.
• the slight doping N could advantageously be a little below, namely in density / concentration between 10 15 and 10 16 cm -3 .
• an HEMT transistor it comprises as shown in FIG. 15:
• a second buffer layer 8 disposed on the first layer 6 and having a thickness determined according to a direction orthogonal to the substrate plane
• Non intentionally doped buffer layer disposed on the second buffer layer 8 and having a thickness determined according to a direction orthogonal to the substrate plane,
• barrier layer 12 disposed on the intermediate layer 1 1, said barrier layer 12 being made of a Ni 2 semiconductor wide bandgap semiconductor material of column III,
• source (S), drain (D) and gate (G) electrodes are source (S), drain (D) and gate (G) electrodes.
• the second P + doped buffer layer 8 is not connected to any transistor electrode, neither the source, nor the drain, nor the gate, whereas this second layer preferably extends over the entire surface of the transistor. In other words, this second P + doped buffer layer 8 is floating.
• gate electrode G is located just above the first region 16 with similar dimensions.
• barrier layer 12 of a nitride-based wide bandgap semiconductor material of column III depositing a barrier layer 12 of a nitride-based wide bandgap semiconductor material of column III on the intermediate layer 11,
• gate (G), drain (D) and source (S) electrodes using one or more layers of electrically conductive materials.
• Drain D and Source S electrodes are so-called “ohmic” contacts thus making contacts metal / semiconductor low resistance and the gate electrode G is a metal contact / semiconductor said "Schottky".
• the method of manufacturing such electrodes being known to those skilled in the art, it will not be detailed in the description.
• the metals used to make these contact resumptions of the HEMT transistor described in the invention can be of different types, depending on the characteristics of the desired contacts.
• the electrodes may be composed of a single layer of metal, for example Ti, Al or other metals, or even bilayer or tri-metallic layer.
• Electrodes can be deposited by the traditional methods of depositing metals used in microelectronics such as for example by the Lift-Off method or the LIGA method (Lithography GAIvanic). Said electrodes may also be made of other materials whose electrical properties have been previously modified to suit the desired contact resistance.
• the invention makes it possible to obtain a HEMT transistor with a zero or positive threshold voltage in order to obtain a "normally OFF" HEMT transistor.
• a first region 16 unintentionally doped allowing the P + doped layer placed under this region to influence the electron gas 2DEG.
• the first region 16 is positioned under the gate electrode (G) of the transistor and is, according to embodiments, 10 nm thick and has a width of 1 ⁇ .
• the first region 16 is characterized by its length Lo16 and its width La16 in a plane parallel to that of the substrate is preferably smaller or equal in size to the dimensions of the gate electrode G in a plane parallel to the plane of the substrate.
• La16 is the width of the first region 16
• LoG is the length of the gate electrode (G), and LaG is the width of the gate electrode (G).
• the placement of the first region 16 with respect to the gate electrode G is important. To do this, the placement of the first region 16 with respect to the gate electrode G must be (FIG. 17 and FIG. 18):
• p1 is the positioning of the gate electrode (G) on the x axis
• p2 is the positioning of the first region 16 on the x axis
• p3 is the positioning of the gate electrode (G) on the x axis z axis
• p4 is the positioning of the first region 16 on the z axis
• B1 is the distance between the gate electrode (G) and the first region 16 along the x axis
• B2 is the distance between the gate electrode (G) and the first region 16 along the z axis
• La16 is the width of the first region 16
• LoG is the length of the gate electrode (G), and,
• LaG is the width of the gate electrode (G).
• the invention proposes to control the threshold voltage of the transistor by varying the distance between the second buffer layer 8 (P + doped) and the AIGaN / GaN interface, that is to say between the layer 1 1 and the barrier layer 12. Indeed, the reduction or increase in the distance between the second buffer layer 8 and the barrier layer 12 makes it possible to modulate the difference between the Fermi level and the conduction band and therefore to modulate the threshold voltage of the transistor.
• the graph of FIG. 19 compares the threshold voltage of a transistor according to an exemplary embodiment of the invention with the threshold voltage of a conventional "normally ON" HEMT having the same physical and geometrical parameters with the exception of the first region 16.
• the parameters of the structure are:
• the thickness of the layer 8 500 nm.
• an oxide layer is integrated in another embodiment between the gate electrode G and the Al (1 - x) GaN layer. This further comprises as shown in FIG. 20:
• a second buffer layer 8 disposed on the first layer 6 and having a thickness determined according to a direction orthogonal to the substrate plane
• Non intentionally doped buffer layer disposed on the second buffer layer 8 and having a thickness determined according to a direction orthogonal to the substrate plane,
• barrier layer 12 disposed on the intermediate layer 1 1, said barrier layer 12 being made of a Ni 2 semiconductor wide bandgap semiconductor material of column III,
• this electrically insulating layer 24 thus makes it possible to obtain a MOS contact for (Metal / Oxide / Semiconductor) between the gate contact G and the barrier layer 12.
• the oxide layer 24 may be obtained by thermal oxidation using, for example, a PECVD (Plasma Enhanced Chemical Vapor Deposition) type oxidation furnace which makes it possible to obtain layers of a few nanometers to a micrometer of thickness, for example.
• PECVD Pulsma Enhanced Chemical Vapor Deposition
• the presence of the oxide layer and the removal of the Schottky contact make it possible to reduce the leakage current of the order, for example, by factor 20, thus making it possible to greatly improve the performance of the HEMT transistor.
• the threshold voltage obtained as a function of the parameters mentioned above makes it possible to obtain a HEMT transistor with a threshold voltage, for example of 4V.
• This positive threshold voltage thus makes it possible to obtain, according to the different embodiments presented, a HEMT transistor which respects the "normally OFF" functionality. New fields of application are possible thanks to such a component. Indeed, this high threshold voltage makes this type of component insensitive to external disturbances such as noise on the gate voltage, including electromagnetic noise.
• the above description has been given for illustrative purposes only and is not limiting of the scope of the invention. Any technically feasible variant embodiment may be preferred to the embodiments described.
• the GaN material used in the description may be replaced by GaAs.
• the use of such a material therefore implies that the type of dopant and the doses that will be used as well as the dimensions and the positioning of the layer 8 will be chosen so that the overall behavior of the HEMT transistor using a GaAs material corresponds to the transistor described in the invention.
• first, second, third, etc. can be used here to describe different elements, components, regions, layers and / or sections. These elements, regions, layers and / or sections should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or section from another region, layer, or section. Thus, a first element, region, layer, or section described above could be referred to as the second element, region, layer, or section without departing from the teachings of inventive concepts.
• the relative positioning terms such as “under”, “below”, “below”, “above”, “above”, etc., have been used here to facilitate description and to describe positioning. of one element with respect to another element as illustrated in the figures.
• the relative positioning terms are intended to cover different orientations of the device according to the invention during use or operation in addition to the orientation shown in the figures. For example, if the device according to the invention is returned, the elements described as “below” or “under” other elements would then be oriented “above” other elements. Thus, the term “below” may encompass both an “above” and “below” orientation. The device may also be otherwise oriented (90 degree rotation or other orientations) and the relative positioning terms used herein will be interpreted accordingly.

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• 2015
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