ES2110960T3 - Procedimiento de planarizacion de topologias en estructuras de circuitos integrados. - Google Patents

Procedimiento de planarizacion de topologias en estructuras de circuitos integrados.

Info

Publication number
ES2110960T3
ES2110960T3 ES90306496T ES90306496T ES2110960T3 ES 2110960 T3 ES2110960 T3 ES 2110960T3 ES 90306496 T ES90306496 T ES 90306496T ES 90306496 T ES90306496 T ES 90306496T ES 2110960 T3 ES2110960 T3 ES 2110960T3
Authority
ES
Spain
Prior art keywords
integrated circuit
oxide layer
circuit structure
parts
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90306496T
Other languages
English (en)
Inventor
Steven C Avanzino
Jacob D Haskell
Subhash Gupta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2110960T3 publication Critical patent/ES2110960T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
    • H10P95/066—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/959—Mechanical polishing of wafer

Landscapes

  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Amplifiers (AREA)
  • Formation Of Insulating Films (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

SE EXPONE UN METODO PARA HACER UNA ESTRUCTURA DE CIRCUITOS INTEGRADOS MUY PLANA QUE TIENE DEPOSITADAS PARTES DE OXIDO PLANAS CON RESPECTO AL NIVEL DE PARTES ADYACENTES DE LA ESTRUCTURA DEL CIRCUITO INTEGRADO, QUE COMPRENDE: DEPOSITAR, SOBRE UNA ESTRUCTURA DE CIRCUITO INTEGRADO QUE TIENE UNAS PRIMERAS PARTES A ALTURA SUPERIOR QUE EL RESTO DE LA ESTRUCTURA DE CIRCUITO INEGRADO, UNA CAPA DE OXIDO CONFORMADO QUE TIENE UN GROSOR QUE EXCEDE LA ALTURA DE LAS CITADAS PRIMERAS PARTES POR ENCIMA DEL RESTO DE LA ESTRUCTURA DEL CIRCUITO INTEGRADO; FORMAR UNA CAPA DE MASCARA CON PATRON SOBRE LA CITADA CAPA DE OXIDO DEPOSITADA CON UNA O MAS APERTURAS EN ESTA A NIVEL CON LAS PRIMERAS PARTES DE ALTURA SUPERIOR DE LA ESTRUCTURA DE CICUITO INTEGRADO; ATACAR QUIMICAMENTE PARTES EXPUESTAS DE LA CITADA CAPA DE OXIDO CONFORMADO A TRAVES DE LOS ORIFICIOS DE LA MASCARA HASTA UN NIVEL APROXIMADAMENTE IGUAL A UN NIVEL DE LA PARTE NO EXPUESTA DE LA CAPA DE OXIDO CONFORMADO ; RETIRAR LA CAPA DE MASCAR; Y PULIMENTAR LACAPA DE OXIDO PARA ELIMINAR LAS PARTES ELEVADAS DE LA CAPA DE OXIDO CONFORMADO QUE SOBRESALGAN DESPUES DE LA OPERACION DE ATAQUE PAR FORMAR UNA ESTRUCTURA MUY PLANA. OPCIONALMENTE, LA CAPA DE OXIDO PUEDE ATACARSE ADEMAS ANISOTROPICAMENTE HASTA QUE SE EXPONGAN LAS SUPERFICIES SUPERIORES DE LA ESTRUCTURA DE CIRCUITO INTEGRADO INFERIOR
ES90306496T 1989-07-03 1990-06-14 Procedimiento de planarizacion de topologias en estructuras de circuitos integrados. Expired - Lifetime ES2110960T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/376,176 US4954459A (en) 1988-05-12 1989-07-03 Method of planarization of topologies in integrated circuit structures

Publications (1)

Publication Number Publication Date
ES2110960T3 true ES2110960T3 (es) 1998-03-01

Family

ID=23484000

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90306496T Expired - Lifetime ES2110960T3 (es) 1989-07-03 1990-06-14 Procedimiento de planarizacion de topologias en estructuras de circuitos integrados.

Country Status (6)

Country Link
US (1) US4954459A (es)
EP (1) EP0407047B9 (es)
JP (1) JPH03116753A (es)
AT (1) ATE161656T1 (es)
DE (1) DE69031849T2 (es)
ES (1) ES2110960T3 (es)

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US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
DE69232648T2 (de) * 1991-11-29 2003-02-06 Sony Corp., Tokio/Tokyo Verfahren zur Herstellung einer Grabenisolation mittels eines Polierschritts und Herstellungsverfahren für eine Halbleitervorrichtung
JP2874486B2 (ja) * 1991-11-29 1999-03-24 ソニー株式会社 ポリッシュ工程を備えたトレンチアイソレーションの形成方法及び半導体装置の製造方法
US5215937A (en) * 1992-05-07 1993-06-01 Advanced Micro Devices, Inc. Optimizing doping control in short channel MOS
US5212106A (en) * 1992-05-07 1993-05-18 Advanced Micro Devices, Inc. Optimizing doping control in short channel MOS
JP3321864B2 (ja) * 1992-11-24 2002-09-09 ヤマハ株式会社 半導体装置とその製法
JP3256623B2 (ja) * 1993-05-28 2002-02-12 株式会社東芝 半導体装置の製造方法
JPH07235537A (ja) * 1994-02-23 1995-09-05 Mitsubishi Electric Corp 表面が平坦化された半導体装置およびその製造方法
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FR2717307B1 (fr) * 1994-03-11 1996-07-19 Maryse Paoli Procede d'isolement de zones actives d'un substrat semi-conducteur par tranchees peu profondes quasi planes, et dispositif correspondant
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FR2734402B1 (fr) * 1995-05-15 1997-07-18 Brouquet Pierre Procede pour l'isolement electrique en micro-electronique, applicable aux cavites etroites, par depot d'oxyde a l'etat visqueux et dispositif correspondant
JP3300203B2 (ja) * 1995-07-04 2002-07-08 松下電器産業株式会社 半導体マスク装置、その製造方法及び半導体装置の製造方法
US5840623A (en) * 1995-10-04 1998-11-24 Advanced Micro Devices, Inc. Efficient and economical method of planarization of multilevel metallization structures in integrated circuits using CMP
JP2687948B2 (ja) * 1995-10-05 1997-12-08 日本電気株式会社 半導体装置の製造方法
US5869385A (en) * 1995-12-08 1999-02-09 Advanced Micro Devices, Inc. Selectively oxidized field oxide region
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US5993686A (en) * 1996-06-06 1999-11-30 Cabot Corporation Fluoride additive containing chemical mechanical polishing slurry and method for use of same
WO1997048132A1 (en) * 1996-06-11 1997-12-18 Advanced Micro Devices, Inc. Method for forming co-planar conductor and insulator features using chemical mechanical planarization
US5851899A (en) * 1996-08-08 1998-12-22 Siemens Aktiengesellschaft Gapfill and planarization process for shallow trench isolation
WO1998007189A1 (en) * 1996-08-13 1998-02-19 Advanced Micro Devices, Inc. Semiconductor trench isolation structure having improved upper surface planarity
US6033596A (en) * 1996-09-24 2000-03-07 Cabot Corporation Multi-oxidizer slurry for chemical mechanical polishing
US5783489A (en) * 1996-09-24 1998-07-21 Cabot Corporation Multi-oxidizer slurry for chemical mechanical polishing
US6039891A (en) 1996-09-24 2000-03-21 Cabot Corporation Multi-oxidizer precursor for chemical mechanical polishing
US6395620B1 (en) * 1996-10-08 2002-05-28 Micron Technology, Inc. Method for forming a planar surface over low density field areas on a semiconductor wafer
US5721172A (en) * 1996-12-02 1998-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers
US6126853A (en) 1996-12-09 2000-10-03 Cabot Microelectronics Corporation Chemical mechanical polishing slurry useful for copper substrates
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US5792707A (en) * 1997-01-27 1998-08-11 Chartered Semiconductor Manufacturing Ltd. Global planarization method for inter level dielectric layers of integrated circuits
US6025270A (en) * 1997-02-03 2000-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Planarization process using tailored etchback and CMP
US5926723A (en) * 1997-03-04 1999-07-20 Advanced Micro Devices, Inc. Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes
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US5880007A (en) * 1997-09-30 1999-03-09 Siemens Aktiengesellschaft Planarization of a non-conformal device layer in semiconductor fabrication
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US6869858B2 (en) * 1999-01-25 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation planarized by wet etchback and chemical mechanical polishing
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US6664190B2 (en) 2001-09-14 2003-12-16 Chartered Semiconductor Manufacturing Ltd. Pre STI-CMP planarization scheme
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Also Published As

Publication number Publication date
EP0407047B1 (en) 1997-12-29
EP0407047A2 (en) 1991-01-09
DE69031849T2 (de) 1998-07-30
DE69031849D1 (de) 1998-02-05
JPH03116753A (ja) 1991-05-17
EP0407047B9 (en) 2005-11-30
US4954459A (en) 1990-09-04
EP0407047A3 (en) 1991-01-30
ATE161656T1 (de) 1998-01-15

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