FR2410364A1 - Procede de fabrication d'avis d'isolement entre des dispositifs semi-conducteurs et dispositifs ainsi obtenus - Google Patents

Procede de fabrication d'avis d'isolement entre des dispositifs semi-conducteurs et dispositifs ainsi obtenus

Info

Publication number
FR2410364A1
FR2410364A1 FR7806167A FR7806167A FR2410364A1 FR 2410364 A1 FR2410364 A1 FR 2410364A1 FR 7806167 A FR7806167 A FR 7806167A FR 7806167 A FR7806167 A FR 7806167A FR 2410364 A1 FR2410364 A1 FR 2410364A1
Authority
FR
France
Prior art keywords
substrate
devices
layer
notice
insulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7806167A
Other languages
English (en)
Other versions
FR2410364B1 (fr
Inventor
Katsutoshi Izumi
Masanobu Doken
Hisashi Ariyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of FR2410364A1 publication Critical patent/FR2410364A1/fr
Application granted granted Critical
Publication of FR2410364B1 publication Critical patent/FR2410364B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H10P30/209—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/03—Manufacture or treatment wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps

Landscapes

  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'INVENTION CONCERNE UN DISPOSITIF SEMI-CONDUCTEUR. SELON L'INVENTION, IL COMPREND UN SUBSTRAT SEMI-CONDUCTEUR 11, UNE PELLICULE ISOLANTE 13 FORMEE A LA SURFACE DU SUBSTRAT, UNE COUCHE COMPOSEE ISOLANTE ET ENFOUIE 15 A UNE PROFONDEUR PREDETERMINEE DE L'AUTRE SURFACE 12 DU SUBSTRAT, LA COUCHE 15 ETANT FORMEE PAR IMPLANTATION D'IONS A TRAVERS LA SURFACE 12, ET DES ELEMENTS SEMI-CONDUCTEURS COMPRENANT UNE COUCHE DU SUBSTRAT ENTRE LA COUCHE COMPOSEE ISOLANTE ENFOUIE ET LA SURFACE 12, LA PELLICULE ISOLANTE 13 FORMEE A LA SURFACE DU SUBSTRAT AYANT UNE EPAISSEUR SUFFISANTE POUR COMPENSER LA CONTRAINTE INDUITE DANS LA COUCHE COMPOSEE ISOLANTE ENFOUIE. L'INVENTION S'APPLIQUE NOTAMMENT A LA FABRICATION DE TRANSISTORS MOS OU BIPOLAIRES.
FR7806167A 1977-11-28 1978-03-03 Procede de fabrication d'avis d'isolement entre des dispositifs semi-conducteurs et dispositifs ainsi obtenus Expired FR2410364B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14159977A JPS5721856B2 (en) 1977-11-28 1977-11-28 Semiconductor and its manufacture

Publications (2)

Publication Number Publication Date
FR2410364A1 true FR2410364A1 (fr) 1979-06-22
FR2410364B1 FR2410364B1 (fr) 1983-01-21

Family

ID=15295748

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7806167A Expired FR2410364B1 (fr) 1977-11-28 1978-03-03 Procede de fabrication d'avis d'isolement entre des dispositifs semi-conducteurs et dispositifs ainsi obtenus

Country Status (7)

Country Link
US (1) US4241359A (fr)
JP (1) JPS5721856B2 (fr)
CA (1) CA1095183A (fr)
DE (1) DE2808257C3 (fr)
FR (1) FR2410364B1 (fr)
GB (1) GB1601676A (fr)
NL (1) NL182999C (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2490874A1 (fr) * 1980-09-19 1982-03-26 Nippon Telegraph & Telephone Transistors du type a grille isolee
FR2491679A1 (fr) * 1980-10-07 1982-04-09 Itt Methode d'isolation d'un dispositif a semi-conducteurs et dispositif ou circuit integre obtenu
FR2525031A1 (fr) * 1982-04-12 1983-10-14 Tokyo Shibaura Electric Co Dispositif a semi-conducteur dont le semi-conducteur est forme sur un substrat isolant et son procede de fabrication
FR2563377A1 (fr) * 1984-04-19 1985-10-25 Commissariat Energie Atomique Procede de fabrication d'une couche isolante enterree dans un substrat semi-conducteur, par implantation ionique
EP0258271A4 (en) * 1986-02-07 1991-03-13 Motorola, Inc. Partially dielectrically isolated semiconductor devices

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5626467A (en) * 1979-08-10 1981-03-14 Toshiba Corp Semiconductor device and the manufacturing process
JPS5662369A (en) * 1979-10-26 1981-05-28 Toshiba Corp Mos semiconductor device
JPS56105652A (en) * 1980-01-28 1981-08-22 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS577161A (en) * 1980-06-16 1982-01-14 Toshiba Corp Mos semiconductor device
JPS5739579A (en) * 1980-08-20 1982-03-04 Toshiba Corp Mos semiconductor device and manufacture thereof
JPS5742161A (en) * 1980-08-28 1982-03-09 Fujitsu Ltd Semiconductor and production thereof
JPS5752167A (en) * 1980-09-16 1982-03-27 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type field effect transistor and manufacture thereof
JPS5854672A (ja) * 1981-09-28 1983-03-31 Fujitsu Ltd 半導体装置
JPS59170555A (ja) * 1983-03-15 1984-09-26 Iseki & Co Ltd 農作業機の動力伝導装置
JPS6035955U (ja) * 1983-08-19 1985-03-12 ヤンマー農機株式会社 農機の無段変速装置
US4686758A (en) * 1984-06-27 1987-08-18 Honeywell Inc. Three-dimensional CMOS using selective epitaxial growth
JPS61177742A (ja) * 1985-02-01 1986-08-09 Mitsubishi Electric Corp 半導体装置
FR2581795B1 (fr) * 1985-05-10 1988-06-17 Golanski Andrzej Procede de fabrication d'une couche isolante continue enterree dans un substrat semi-conducteur, par implantation ionique
US4717677A (en) * 1985-08-19 1988-01-05 Motorola Inc. Fabricating a semiconductor device with buried oxide
US4662059A (en) * 1985-09-19 1987-05-05 Rca Corporation Method of making stabilized silicon-on-insulator field-effect transistors having 100 oriented side and top surfaces
US4700454A (en) * 1985-11-04 1987-10-20 Intel Corporation Process for forming MOS transistor with buried oxide regions for insulation
JPS632350A (ja) * 1986-06-20 1988-01-07 Fujitsu Ltd 半導体装置の製造方法
US5043778A (en) * 1986-08-11 1991-08-27 Texas Instruments Incorporated Oxide-isolated source/drain transistor
US4862232A (en) * 1986-09-22 1989-08-29 General Motors Corporation Transistor structure for high temperature logic circuits with insulation around source and drain regions
JPS63119218A (ja) * 1986-11-07 1988-05-23 Canon Inc 半導体基材とその製造方法
JPS63157475A (ja) * 1986-12-20 1988-06-30 Toshiba Corp 半導体装置及びその製造方法
US5115289A (en) * 1988-11-21 1992-05-19 Hitachi, Ltd. Semiconductor device and semiconductor memory device
US5080730A (en) * 1989-04-24 1992-01-14 Ibis Technology Corporation Implantation profile control with surface sputtering
WO1992005580A1 (fr) * 1990-09-14 1992-04-02 Westinghouse Electric Corporation Circuit hybride hyperfrequence monolithique fabrique sur une tranche de silicium a haute resistivite
US6884701B2 (en) * 1991-04-27 2005-04-26 Hidemi Takasu Process for fabricating semiconductor device
KR960002765B1 (ko) * 1992-12-22 1996-02-26 금성일렉트론주식회사 절연체 위에 단결정 반도체 제조방법
US6228779B1 (en) 1998-11-06 2001-05-08 Novellus Systems, Inc. Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology
US6383924B1 (en) 2000-12-13 2002-05-07 Micron Technology, Inc. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US7142577B2 (en) 2001-05-16 2006-11-28 Micron Technology, Inc. Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon
US6898362B2 (en) * 2002-01-17 2005-05-24 Micron Technology Inc. Three-dimensional photonic crystal waveguide structure and method
US7041575B2 (en) * 2003-04-29 2006-05-09 Micron Technology, Inc. Localized strained semiconductor on insulator
US6987037B2 (en) * 2003-05-07 2006-01-17 Micron Technology, Inc. Strained Si/SiGe structures by ion implantation
US7501329B2 (en) 2003-05-21 2009-03-10 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US7662701B2 (en) 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US7273788B2 (en) 2003-05-21 2007-09-25 Micron Technology, Inc. Ultra-thin semiconductors bonded on glass substrates
US7008854B2 (en) 2003-05-21 2006-03-07 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US7439158B2 (en) 2003-07-21 2008-10-21 Micron Technology, Inc. Strained semiconductor by full wafer bonding
US6929984B2 (en) * 2003-07-21 2005-08-16 Micron Technology Inc. Gettering using voids formed by surface transformation
US7153753B2 (en) 2003-08-05 2006-12-26 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US7396779B2 (en) * 2003-09-24 2008-07-08 Micron Technology, Inc. Electronic apparatus, silicon-on-insulator integrated circuits, and fabrication methods
KR100604527B1 (ko) * 2003-12-31 2006-07-24 동부일렉트로닉스 주식회사 바이폴라 트랜지스터 제조방법
US7544584B2 (en) 2006-02-16 2009-06-09 Micron Technology, Inc. Localized compressive strained semiconductor

Citations (2)

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Publication number Priority date Publication date Assignee Title
US3622382A (en) * 1969-05-05 1971-11-23 Ibm Semiconductor isolation structure and method of producing
US3976511A (en) * 1975-06-30 1976-08-24 Ibm Corporation Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment

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US3666548A (en) * 1970-01-06 1972-05-30 Ibm Monocrystalline semiconductor body having dielectrically isolated regions and method of forming
US3840409A (en) * 1970-03-16 1974-10-08 Ibm Insulating layer pedestal transistor device and process
US3707765A (en) * 1970-11-19 1973-01-02 Motorola Inc Method of making isolated semiconductor devices
BE792589A (fr) * 1971-10-06 1973-03-30 Ibm Procede d'obtention de structures semiconductrices par implantation d'ions
US3791024A (en) * 1971-10-21 1974-02-12 Rca Corp Fabrication of monolithic integrated circuits
US3873373A (en) * 1972-07-06 1975-03-25 Bryan H Hill Fabrication of a semiconductor device
US3886587A (en) * 1973-07-19 1975-05-27 Harris Corp Isolated photodiode array
US3855009A (en) * 1973-09-20 1974-12-17 Texas Instruments Inc Ion-implantation and conventional epitaxy to produce dielectrically isolated silicon layers
JPS5068072A (fr) * 1973-10-17 1975-06-07
JPS5329551B2 (fr) * 1974-08-19 1978-08-22
JPS6041458B2 (ja) * 1975-04-21 1985-09-17 ソニー株式会社 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3622382A (en) * 1969-05-05 1971-11-23 Ibm Semiconductor isolation structure and method of producing
US3976511A (en) * 1975-06-30 1976-08-24 Ibm Corporation Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
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EXBK/73 *
NV700/74 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2490874A1 (fr) * 1980-09-19 1982-03-26 Nippon Telegraph & Telephone Transistors du type a grille isolee
FR2491679A1 (fr) * 1980-10-07 1982-04-09 Itt Methode d'isolation d'un dispositif a semi-conducteurs et dispositif ou circuit integre obtenu
FR2525031A1 (fr) * 1982-04-12 1983-10-14 Tokyo Shibaura Electric Co Dispositif a semi-conducteur dont le semi-conducteur est forme sur un substrat isolant et son procede de fabrication
FR2563377A1 (fr) * 1984-04-19 1985-10-25 Commissariat Energie Atomique Procede de fabrication d'une couche isolante enterree dans un substrat semi-conducteur, par implantation ionique
EP0164281A1 (fr) * 1984-04-19 1985-12-11 Commissariat A L'energie Atomique Procédé de fabrication d'une couche isolante enterrée dans un substrat semiconducteur, par implantation ionique
US4704302A (en) * 1984-04-19 1987-11-03 Commissariat A L'energie Atomique Process for producing an insulating layer buried in a semiconductor substrate by ion implantation
EP0258271A4 (en) * 1986-02-07 1991-03-13 Motorola, Inc. Partially dielectrically isolated semiconductor devices

Also Published As

Publication number Publication date
CA1095183A (fr) 1981-02-03
JPS5474682A (en) 1979-06-14
GB1601676A (en) 1981-11-04
DE2808257A1 (de) 1979-05-31
DE2808257B2 (de) 1981-02-19
JPS5721856B2 (en) 1982-05-10
NL7802260A (nl) 1979-05-30
NL182999C (nl) 1988-06-16
DE2808257C3 (de) 1981-12-24
FR2410364B1 (fr) 1983-01-21
US4241359A (en) 1980-12-23

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