JP4809510B2 - 部分的に作製された金属酸化物半導体デバイスのゲート酸化物を硬化させる方法 - Google Patents

部分的に作製された金属酸化物半導体デバイスのゲート酸化物を硬化させる方法 Download PDF

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Publication number
JP4809510B2
JP4809510B2 JP30441398A JP30441398A JP4809510B2 JP 4809510 B2 JP4809510 B2 JP 4809510B2 JP 30441398 A JP30441398 A JP 30441398A JP 30441398 A JP30441398 A JP 30441398A JP 4809510 B2 JP4809510 B2 JP 4809510B2
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Prior art keywords
polysilicon layer
polysilicon
gate oxide
nitrogen concentration
layer
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Expired - Fee Related
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JP30441398A
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English (en)
Japanese (ja)
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JPH11204793A5 (2
JPH11204793A (ja
Inventor
シュー−リュエン・ワン
チャン−シェン・ヤオ
ウェン−チン・イー
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LSI Corp
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LSI Logic Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01338—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
JP30441398A 1997-10-24 1998-10-26 部分的に作製された金属酸化物半導体デバイスのゲート酸化物を硬化させる方法 Expired - Fee Related JP4809510B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/957,692 US6017808A (en) 1997-10-24 1997-10-24 Nitrogen implanted polysilicon gate for MOSFET gate oxide hardening
US957692 1997-10-24

Publications (3)

Publication Number Publication Date
JPH11204793A JPH11204793A (ja) 1999-07-30
JPH11204793A5 JPH11204793A5 (2) 2005-12-08
JP4809510B2 true JP4809510B2 (ja) 2011-11-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP30441398A Expired - Fee Related JP4809510B2 (ja) 1997-10-24 1998-10-26 部分的に作製された金属酸化物半導体デバイスのゲート酸化物を硬化させる方法

Country Status (2)

Country Link
US (1) US6017808A (2)
JP (1) JP4809510B2 (2)

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US6815295B1 (en) * 1997-05-14 2004-11-09 Renesas Technology Corp. Method of manufacturing field effect transistors
US6989319B1 (en) 1998-08-28 2006-01-24 Advanced Micro Devices, Inc. Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices
US6245652B1 (en) * 1998-09-04 2001-06-12 Advanced Micro Devices, Inc. Method of forming ultra thin gate dielectric for high performance semiconductor devices
US6221724B1 (en) * 1998-11-06 2001-04-24 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit having punch-through suppression
US6342438B2 (en) * 1998-11-06 2002-01-29 Advanced Micro Devices, Inc. Method of manufacturing a dual doped CMOS gate
US6265291B1 (en) 1999-01-04 2001-07-24 Advanced Micro Devices, Inc. Circuit fabrication method which optimizes source/drain contact resistance
US6329670B1 (en) * 1999-04-06 2001-12-11 Micron Technology, Inc. Conductive material for integrated circuit fabrication
JP2001093903A (ja) * 1999-09-24 2001-04-06 Toshiba Corp 半導体装置及びその製造方法
US6277719B1 (en) * 1999-11-15 2001-08-21 Vanguard International Semiconductor Corporation Method for fabricating a low resistance Poly-Si/metal gate
US6559007B1 (en) * 2000-04-06 2003-05-06 Micron Technology, Inc. Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide
US6342437B1 (en) * 2000-06-01 2002-01-29 Micron Technology, Inc. Transistor and method of making the same
US6514825B1 (en) * 2000-06-28 2003-02-04 Conexant Systems, Inc. Technique for reducing 1/f noise in MOSFETs
US6399450B1 (en) 2000-07-05 2002-06-04 Advanced Micro Devices, Inc. Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions
US6458663B1 (en) * 2000-08-17 2002-10-01 Micron Technology, Inc. Masked nitrogen enhanced gate oxide
US6544908B1 (en) 2000-08-30 2003-04-08 Micron Technology, Inc. Ammonia gas passivation on nitride encapsulated devices
TW531803B (en) * 2000-08-31 2003-05-11 Agere Syst Guardian Corp Electronic circuit structure with improved dielectric properties
KR100451036B1 (ko) * 2000-12-08 2004-10-02 주식회사 하이닉스반도체 반도체 소자의 게이트 전극 형성 방법
US6551885B1 (en) 2001-02-09 2003-04-22 Advanced Micro Devices, Inc. Low temperature process for a thin film transistor
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6756277B1 (en) 2001-02-09 2004-06-29 Advanced Micro Devices, Inc. Replacement gate process for transistors having elevated source and drain regions
US6495437B1 (en) 2001-02-09 2002-12-17 Advanced Micro Devices, Inc. Low temperature process to locally form high-k gate dielectrics
US6787424B1 (en) 2001-02-09 2004-09-07 Advanced Micro Devices, Inc. Fully depleted SOI transistor with elevated source and drain
AU2002347561A1 (en) * 2001-12-20 2003-07-09 Koninklijke Philips Electronics N.V. Method of introducing nitrogen into semiconductor dielectric layers
KR20030054854A (ko) * 2001-12-26 2003-07-02 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR100824661B1 (ko) * 2001-12-28 2008-04-25 매그나칩 반도체 유한회사 반도체 소자의 제조방법
DE10234488B4 (de) * 2002-07-29 2007-03-29 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer lokalisierten Implantationsbarriere in einer Polysiliziumleitung
US7314812B2 (en) * 2003-08-28 2008-01-01 Micron Technology, Inc. Method for reducing the effective thickness of gate oxides by nitrogen implantation and anneal
US7312125B1 (en) 2004-02-05 2007-12-25 Advanced Micro Devices, Inc. Fully depleted strained semiconductor on insulator transistor and method of making the same
US7271079B2 (en) * 2005-04-06 2007-09-18 International Business Machines Corporation Method of doping a gate electrode of a field effect transistor
JP2007188969A (ja) * 2006-01-11 2007-07-26 Toshiba Corp 半導体装置およびその製造方法
JP2007220755A (ja) * 2006-02-14 2007-08-30 Toshiba Corp 半導体装置及びその製造方法
US7754545B2 (en) * 2007-12-03 2010-07-13 Macronix International Co., Ltd. Semiconductor device and method of fabricating the same
US7736968B2 (en) * 2008-10-27 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing poly-depletion through co-implanting carbon and nitrogen
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US6017808A (en) 2000-01-25

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