JPH01100240U - - Google Patents

Info

Publication number
JPH01100240U
JPH01100240U JP19342687U JP19342687U JPH01100240U JP H01100240 U JPH01100240 U JP H01100240U JP 19342687 U JP19342687 U JP 19342687U JP 19342687 U JP19342687 U JP 19342687U JP H01100240 U JPH01100240 U JP H01100240U
Authority
JP
Japan
Prior art keywords
signal
memory
processing unit
central processing
selection device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19342687U
Other languages
English (en)
Other versions
JPH0435957Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987193426U priority Critical patent/JPH0435957Y2/ja
Publication of JPH01100240U publication Critical patent/JPH01100240U/ja
Application granted granted Critical
Publication of JPH0435957Y2 publication Critical patent/JPH0435957Y2/ja
Expired legal-status Critical Current

Links

Description

【図面の簡単な説明】
第１図はこの考案に係るメモリ選択装置の周辺
の構成を示す構成図、第２図は従来のメモリ選択
装置の周辺の構成を示す構成図である。 １……中央処理装置、２……メモリ、３……デ
コーダ、４……論理回路、４１……ＯＲ回路、４
２……ＡＮＤ回路。

Claims (1)

  1. 【実用新案登録請求の範囲】 中央処理装置から出力されるアドレス信号をデ
    コードしてデコード信号を作り出し、このデコー
    ド信号からメモリのチツプセレクト信号を作り出
    すメモリ選択装置において、 中央処理装置から出力されるメモリの読書き制
    御用信号と少なくとも１つのアドレス信号と上記
    デコード信号との論理を演算してチツプセレクト
    信号を作り出す論理回路を付加したことを特徴と
    するメモリ選択装置。
JP1987193426U 1987-12-22 1987-12-22 Expired JPH0435957Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987193426U JPH0435957Y2 (ja) 1987-12-22 1987-12-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987193426U JPH0435957Y2 (ja) 1987-12-22 1987-12-22

Publications (2)

Publication Number Publication Date
JPH01100240U true JPH01100240U (ja) 1989-07-05
JPH0435957Y2 JPH0435957Y2 (ja) 1992-08-25

Family

ID=31484214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987193426U Expired JPH0435957Y2 (ja) 1987-12-22 1987-12-22

Country Status (1)

Country Link
JP (1) JPH0435957Y2 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57172589A (en) * 1981-04-15 1982-10-23 Nec Corp Memory access circuit
JPS5837756A (ja) * 1981-08-31 1983-03-05 Ricoh Co Ltd メモリ制御装置
JPS60250454A (ja) * 1984-05-25 1985-12-11 Yokogawa Hokushin Electric Corp メモリ制御装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57172589A (en) * 1981-04-15 1982-10-23 Nec Corp Memory access circuit
JPS5837756A (ja) * 1981-08-31 1983-03-05 Ricoh Co Ltd メモリ制御装置
JPS60250454A (ja) * 1984-05-25 1985-12-11 Yokogawa Hokushin Electric Corp メモリ制御装置

Also Published As

Publication number Publication date
JPH0435957Y2 (ja) 1992-08-25

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