JPH01100443U - - Google Patents
Info
- Publication number
- JPH01100443U JPH01100443U JP1987195704U JP19570487U JPH01100443U JP H01100443 U JPH01100443 U JP H01100443U JP 1987195704 U JP1987195704 U JP 1987195704U JP 19570487 U JP19570487 U JP 19570487U JP H01100443 U JPH01100443 U JP H01100443U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- insulating resin
- electrode
- groove
- covers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案における半導体装置の実装構造
を示す平面図、第2図a〜cは本考案における第
1の実施例における構成を得るための工程を説明
する第1図のA―A断面図、第2図dは第2図c
に対応する斜視図、第3図a〜cは本考案におけ
る第2の実施例における構成を得るための工程を
説明する断面図、第4図は従来例における半導体
装置の実装構造を示す断面図、第5図および第6
図はいずれも従来例における半導体装置の実装構
造を示す平面図である。
1……半導体装置(IC)、3……絶縁樹脂、
4……導体、5……プラスチツク保護板、9……
凹溝。
FIG. 1 is a plan view showing the mounting structure of a semiconductor device according to the present invention, and FIGS. 2 a to c are cross sections taken along line A-A in FIG. Figure 2d is Figure 2c
FIGS. 3a to 3c are sectional views illustrating the steps for obtaining the configuration of the second embodiment of the present invention, and FIG. 4 is a sectional view showing the mounting structure of a semiconductor device in a conventional example. , Figures 5 and 6
Each figure is a plan view showing a mounting structure of a semiconductor device in a conventional example. 1... Semiconductor device (IC), 3... Insulating resin,
4...Conductor, 5...Plastic protection plate, 9...
Concave groove.
Claims (1)
う絶縁樹脂と、前記電極に対応して前記絶縁樹脂
に設ける凹溝と、該凹溝に形成する導体とからな
ることを特徴とする半導体装置の実装構造。 A semiconductor device package comprising: an insulating resin that covers a semiconductor device so that only electrode portions are exposed; a groove provided in the insulating resin corresponding to the electrode; and a conductor formed in the groove. structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987195704U JPH06821Y2 (en) | 1987-12-25 | 1987-12-25 | Semiconductor device mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987195704U JPH06821Y2 (en) | 1987-12-25 | 1987-12-25 | Semiconductor device mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01100443U true JPH01100443U (en) | 1989-07-05 |
| JPH06821Y2 JPH06821Y2 (en) | 1994-01-05 |
Family
ID=31486366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987195704U Expired - Lifetime JPH06821Y2 (en) | 1987-12-25 | 1987-12-25 | Semiconductor device mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06821Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011009408A (en) * | 2009-06-25 | 2011-01-13 | Ricoh Co Ltd | Electronic component module and manufacturing method |
| JP2018093221A (en) * | 2016-09-26 | 2018-06-14 | 株式会社パウデック | Semiconductor package, module, and electric device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4834674A (en) * | 1971-09-09 | 1973-05-21 | ||
| JPS61220346A (en) * | 1985-03-26 | 1986-09-30 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1987
- 1987-12-25 JP JP1987195704U patent/JPH06821Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4834674A (en) * | 1971-09-09 | 1973-05-21 | ||
| JPS61220346A (en) * | 1985-03-26 | 1986-09-30 | Toshiba Corp | Semiconductor device and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011009408A (en) * | 2009-06-25 | 2011-01-13 | Ricoh Co Ltd | Electronic component module and manufacturing method |
| JP2018093221A (en) * | 2016-09-26 | 2018-06-14 | 株式会社パウデック | Semiconductor package, module, and electric device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06821Y2 (en) | 1994-01-05 |