JPH01104721U - - Google Patents

Info

Publication number
JPH01104721U
JPH01104721U JP1988000402U JP40288U JPH01104721U JP H01104721 U JPH01104721 U JP H01104721U JP 1988000402 U JP1988000402 U JP 1988000402U JP 40288 U JP40288 U JP 40288U JP H01104721 U JPH01104721 U JP H01104721U
Authority
JP
Japan
Prior art keywords
pellet
lead frame
folding
semiconductor device
high frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988000402U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988000402U priority Critical patent/JPH01104721U/ja
Publication of JPH01104721U publication Critical patent/JPH01104721U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図、第3図はそれぞれ本考案の実施例を示
す断面図、第2図は第1図の側面断面図、第4図
は第3図の内部透視図、第5図は従来の半導体素
子の断面図である。 1……リードフレーム、2……ペレツト、3…
…ボンデイングパツド、4……ボンデイング線、
5……樹脂。

Claims (1)

    【実用新案登録請求の範囲】
  1. ペレツト上の各ボンデイングパツドとリードフ
    レームの間を1本の金属細線で折り返し接続する
    ことにより、複数のボンデイング線を有すること
    を特徴とする高周波半導体装置。
JP1988000402U 1988-01-05 1988-01-05 Pending JPH01104721U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988000402U JPH01104721U (ja) 1988-01-05 1988-01-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988000402U JPH01104721U (ja) 1988-01-05 1988-01-05

Publications (1)

Publication Number Publication Date
JPH01104721U true JPH01104721U (ja) 1989-07-14

Family

ID=31199395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988000402U Pending JPH01104721U (ja) 1988-01-05 1988-01-05

Country Status (1)

Country Link
JP (1) JPH01104721U (ja)

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