JPH01108940U - - Google Patents

Info

Publication number
JPH01108940U
JPH01108940U JP1988002710U JP271088U JPH01108940U JP H01108940 U JPH01108940 U JP H01108940U JP 1988002710 U JP1988002710 U JP 1988002710U JP 271088 U JP271088 U JP 271088U JP H01108940 U JPH01108940 U JP H01108940U
Authority
JP
Japan
Prior art keywords
substrate
chip
utility
sealed
model
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988002710U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988002710U priority Critical patent/JPH01108940U/ja
Publication of JPH01108940U publication Critical patent/JPH01108940U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図ないし第５図は本考案によるＩＣボード
の実施例を示す概略的断面図である。 １，１２…合成シリカ基板、２…２５６Ｋビツ
トＤＲＡＭのベヤチツプ、７，８，１０…樹脂、
９…シリカ基板。

Claims (1)

  1. 【実用新案登録請求の範囲】 基板と、該基板に搭載されたＩＣチツプとを有
    し、該ＩＣチツプは、その電極部に予め形成され
    た半田バンプによつて上記基板の導体部に接続さ
    れてなるＩＣボードにおいて、 上記基板はシリカ基板であり、上記ＩＣチツプ
    は気密封止又は弾性率が５００Kgｆ／mm2以下の
    樹脂で封止されていることを特徴とするＩＣボー
    ド。
JP1988002710U 1988-01-13 1988-01-13 Pending JPH01108940U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988002710U JPH01108940U (ja) 1988-01-13 1988-01-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988002710U JPH01108940U (ja) 1988-01-13 1988-01-13

Publications (1)

Publication Number Publication Date
JPH01108940U true JPH01108940U (ja) 1989-07-24

Family

ID=31203715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988002710U Pending JPH01108940U (ja) 1988-01-13 1988-01-13

Country Status (1)

Country Link
JP (1) JPH01108940U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100467897B1 (ko) * 1996-12-24 2005-01-24 닛토덴코 가부시키가이샤 반도체 장치 및 이의 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100467897B1 (ko) * 1996-12-24 2005-01-24 닛토덴코 가부시키가이샤 반도체 장치 및 이의 제조방법

Similar Documents

Publication Publication Date Title
JPH0270447U (ja)
JPS60163751U (ja) 半導体装置
JPH0390327U (ja)
JPH022835U (ja)
JPS6115746U (ja) 集積回路用パツケ−ジ
JPS60106375U (ja) 外部リ−ド端子の取付構造
JPH024261U (ja)
JPH0217854U (ja)
JPH0351870U (ja)
JPS62112144U (ja)
JPS62163956U (ja)
JPS6219751U (ja)
JPH0221745U (ja)
JPS60158788U (ja) 時計におけるｉｃ保護構造
JPH01162255U (ja)
JPH0179843U (ja)
JPS6096831U (ja) 半導体チツプ
JPS60132028U (ja) 弾性表面波素子
JPS60145583U (ja) 集積回路用ソケツト
JPS6430878U (ja)
JPH0442732U (ja)
JPS63127168U (ja)
JPS6265847U (ja)
JPS60151137U (ja) チツプキヤリア
JPS6196558U (ja)