JPH0167746U - - Google Patents

Info

Publication number
JPH0167746U
JPH0167746U JP1987162909U JP16290987U JPH0167746U JP H0167746 U JPH0167746 U JP H0167746U JP 1987162909 U JP1987162909 U JP 1987162909U JP 16290987 U JP16290987 U JP 16290987U JP H0167746 U JPH0167746 U JP H0167746U
Authority
JP
Japan
Prior art keywords
semiconductor device
wiring board
flip
utility
registration request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987162909U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987162909U priority Critical patent/JPH0167746U/ja
Publication of JPH0167746U publication Critical patent/JPH0167746U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示すＩＣと、これ
を実装するためのプリント基板の要部を示す側断
面図、第２図は上記両者を接合した状態を示す側
断面図、第３図は多重膜の層構成の例を示す図で
ある。 １：ＩＣ、２：ＩＣ１のパツド、３；ＩＣ１の
保護層、４：多重膜、５：プリント基板、６：プ
リント基板５のパツド、７：プリント基板の保護
層、８：半田バンプ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 配線基板上にフリツプチツプボンデイングを行
    う半導体装置において、半田バンプは前記配線基
    板側にのみ形成し、半導体装置のボンデイングパ
    ツドには、金属多重層のみを形成したことを特徴
    とする半導体装置。
JP1987162909U 1987-10-23 1987-10-23 Pending JPH0167746U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987162909U JPH0167746U (ja) 1987-10-23 1987-10-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987162909U JPH0167746U (ja) 1987-10-23 1987-10-23

Publications (1)

Publication Number Publication Date
JPH0167746U true JPH0167746U (ja) 1989-05-01

Family

ID=31447164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987162909U Pending JPH0167746U (ja) 1987-10-23 1987-10-23

Country Status (1)

Country Link
JP (1) JPH0167746U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04282836A (ja) * 1990-10-22 1992-10-07 Internatl Business Mach Corp <Ibm> 薄膜積層体における障壁の改良

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04282836A (ja) * 1990-10-22 1992-10-07 Internatl Business Mach Corp <Ibm> 薄膜積層体における障壁の改良

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