JPH0197559U - - Google Patents

Info

Publication number
JPH0197559U
JPH0197559U JP19429887U JP19429887U JPH0197559U JP H0197559 U JPH0197559 U JP H0197559U JP 19429887 U JP19429887 U JP 19429887U JP 19429887 U JP19429887 U JP 19429887U JP H0197559 U JPH0197559 U JP H0197559U
Authority
JP
Japan
Prior art keywords
resin
sealed semiconductor
sectional
view
white
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19429887U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19429887U priority Critical patent/JPH0197559U/ja
Publication of JPH0197559U publication Critical patent/JPH0197559U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の樹脂封止半導体集
積回路の縦断面図、第2図は本考案の他の実施例
のミニモールド型トランジスタの縦断面図、第3
図は従来の樹脂封止半導体集積回路の縦断面図、
第4図は赤外線リフローによる面実装時の温度プ
ロフアイルを反射板を使用する場合と使用しない
場合とで示したグラフである。 1……表面カバー、2……パツケージ、3……
外部リード、4……半田、5……基板。
FIG. 1 is a vertical cross-sectional view of a resin-sealed semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a mini-mold type transistor according to another embodiment of the present invention, and FIG.
The figure is a longitudinal cross-sectional view of a conventional resin-sealed semiconductor integrated circuit.
FIG. 4 is a graph showing the temperature profile during surface mounting by infrared reflow with and without a reflector. 1... Surface cover, 2... Package cage, 3...
External lead, 4...solder, 5...board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子を封止する樹脂パツケージの表面が
白色系又は光沢色の被膜で覆われていることを特
徴とする樹脂封止半導体装置。
A resin-sealed semiconductor device characterized in that the surface of a resin package for sealing a semiconductor element is covered with a white or glossy coating.
JP19429887U 1987-12-21 1987-12-21 Pending JPH0197559U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19429887U JPH0197559U (en) 1987-12-21 1987-12-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19429887U JPH0197559U (en) 1987-12-21 1987-12-21

Publications (1)

Publication Number Publication Date
JPH0197559U true JPH0197559U (en) 1989-06-29

Family

ID=31485032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19429887U Pending JPH0197559U (en) 1987-12-21 1987-12-21

Country Status (1)

Country Link
JP (1) JPH0197559U (en)

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