JPH0223633A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To perform pattern designs for each mat and realize optionally the whole layout of an IC through combination of mats where respective designs are complete by housing respective circuit blocks in regions consisting of integral pieces of the mats after causing the mats to be made the base of the whole layout of the IC. CONSTITUTION:A dividing region 12 which crosses a semiconductor chip 11 almost linearly is formed at the center of its chip and then, the chip is divided into two regions, such as the first and second regions 13 and 14. The above regions are divided substantially into the regions having the same sizes by providing a plurality of demarcation lines 37 in parallel and then, such a region acts as a mat 18. Housing of respective circuit blocks in the integral pieces of mats allows each circuit not only to perform its design for each block but also to perform the design for each mat 18 after dividing each circuit block into a prescribed number of elements. Designs in parallel for respective circuit blocks are thus carried out and the period required for designs is drastically shortened. As even circuit change is performed for each circuit block as well as for each mat, it is unnecessary to perform the entire design change of ICs.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor integrated circuit in which circuit blocks such as an FM/AM tuner having different signal frequencies and signal levels are formed on the same semiconductor substrate.

(b) Conventional technology Electronic devices such as TV tuners and FA/AM tuners are
Since the audio signal is extracted from the F (Radio Frequency) signal, the frequency of the signal handled by each functionally divided circuit block is often different.

For example, an FM tuner for Japan only has an RF multiplied signal of 76 to 90 MHz and an intermediate frequency signal of 10°7 M)
1z, and audio signals of 20 to 20,000 Hz, and each circuit block handles any signal of 20 Hz to 90 MHz.

An example of the above FM/AM tuner is shown in FIG. In the figure, (1) is an FM front-end circuit that selects FM broadcasting and converts the frequency to an intermediate frequency, and (2) is an FM front-end circuit that detects an intermediate frequency signal (IF multiplied signal and obtains an audio signal (AF multiplied signal). Amplification circuit (3) is for example
- Noise canceling circuit having the function as described in No. 21461, (4) is L in the case of stereo broadcasting.
(5) is an AM tuner circuit that selects AM broadcasting and outputs an audio signal. For example, in the case of FM broadcast reception, the RF signal input from the antenna (6) and the oscillation frequency signal output from the local oscillation circuit of the FM front end circuit (1) are mixed by the mixer of the FM front end circuit (1). The IF multiplied signal is output from the FM front end circuit <1), and the IF multiplied signal is outputted from the FM/IF amplification circuit (
A composite signal is output from the FM-IF amplifier circuit (2) by detection by the detection circuit 2), and the audio signals of the L channel and R channel are respectively output to the output terminal (7) by the multiplex circuit (4). It is configured to output. The FM tuner circuit with such a configuration is described in, for example, "Sanyo Semiconductor Data Book Portable Audio Bipolar Integrated Circuits Edition" published on December 10, 1988, Volume 1.
It is described on page 52.

By the way, electronic devices in recent years are required to be smaller and more sophisticated, and as a result, the circuit shown in Figure 5 is being integrated into a single chip as much as possible. There are various demands such as deletion, replacement, and addition of specific circuit blocks to the circuit shown in FIG.

Therefore, when trying to meet each request, the specific circuit block cannot necessarily be accommodated within the same occupied area, so the design must be redesigned for each request. The drawback was that it was not possible to respond immediately. In addition, in the above example of the FM tuner, the FM front end circuit (1) handles high frequency signals of several tens of MHz, so the ground (
Signal interference due to common impedance due to sharing part of GND) wiring or power supply (Vcc) wiring, interference through semiconductor substrates, and interference due to leakage current due to parasitic transistor effects are likely to occur, making it difficult to integrate into a single chip. There was a certain drawback.

As a conventional technique of this kind, for example, Japanese Patent Application Laid-Open No. 59-84
There is a technique described in No. 542 (HOI L 21/76). That is, each circuit block where interference is likely to occur is divided by a highly concentrated isolation region connected to the semiconductor substrate, and a ground wiring is extended on the surface of the isolation region, and this ground wiring is brought into ohmic contact with the isolation region to connect the substrate. This is a so-called extraction electrode technology that sucks out leakage current. However, even in this example, when deleting, replacing, or adding the circuit blocks mentioned above, it is necessary to rebuild the building from the beginning, which has the disadvantage that it is not possible to respond immediately to requests, and that it takes a long design time to develop models. . Further, even if a suction electrode is provided, a potential difference occurs due to the impedance of the ground wiring, and it is impossible to completely eliminate interference between circuit blocks.

(c) Problems to be Solved by the Invention As described above, conventional bipolar ICs have the disadvantage that when a specific circuit block is deleted, replaced, or added, the pattern design cannot be immediately adapted, resulting in a long development period. Further, when ICs are made to have more functions and high frequency circuits are integrated into a single chip, there is a drawback that interference tends to occur between each circuit block.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and consists of a divided region 12 that crosses the center of the semiconductor chip (11) in a substantially straight line.
) to connect the semiconductor chip 1) to the first and second regions (1).
3) and (14) and extend the power line (15> and ground line (16) to separate them into mats <18> of the same size, and connect the power line on the divided area (12). (15) and a plurality of ground lines (16>), and the separation area (2) is provided in the divided area (12).
4) is characterized in that the dummy islands (21) surrounded by dummy islands (21) are formed in single or multiple layers.

(E) Effect According to the present invention, each circuit block is stored in an integral number of mats (18), so when deleting, replacing, or adding a specific circuit block, each mat 8) can be arbitrarily treated as one unit. You can move to Therefore, the design change was made with a changed mat (
Connections between circuit elements housed in 18) and each mat (18)
Since all you need to do is change the wiring between the two, the design period can be shortened. In addition, the power line (15) or ground line (1
By extending 6), a dummy island (21) is provided in the divided area (12) that requires a relatively large area, thereby reducing interference due to leakage current when high frequency circuits coexist without increasing the chip size. can be prevented.

Kube) Example Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a plan view showing a semiconductor integrated circuit of the present invention.

First, a divided region (12) is formed in the center of the semiconductor chip (11) and crosses it in a substantially straight line, and the semiconductor chip (11)
The element forming region is divided into two regions of substantially the same size, upper and lower. The divided area (12) is an area for extending wiring, which will be described later, and is an area in which no circuit elements are formed. and the second area (13) (1
4). A power supply ■ is shown by a solid line in the figure in a direction perpendicular to the extending direction of the divided region (12). The ground line (1
6) and a partition line (17) extending in pairs,
By arranging a plurality of partition lines (17) in parallel, the first
and the second regions (13) and (14) are divided into regions of substantially the same size, and each region is defined as a mat (18). The size of the mat (18) is set to a size that allows an arbitrary fixed number of elements to be laid out.

On both sides of the mat (18), the VccC line 15) and the ground line (16), which constitute the partition line (17), extend in pairs, so by arranging them regularly, the mat (18) can be V on one side. . line (15)
However, the ground lines (16) are extended so as to be in contact with the other opposing sides. And 1 of Matt (18)
■ Extending to one side and the other side. The C line (15) and the ground line (16) supply operating power to the circuit elements housed within the mat (18).

■Extended section line (17). . The line (15) and ground line (16) are grouped by purpose or by each circuit block, extend over the divided area (12), and each has a corresponding V. . They are individually connected to the electrode pad (19) or the ground electrode pad (20). V summarized. Since the C line (15) and the ground line (16) are formed relatively wide to reduce the impedance of the wiring, a divided area (12) where multiple of these wirings are arranged in parallel is used.
requires a relatively large footprint.

VCC line (15) and ground line (16) that extend the division line (17), CC line (15) and ground line (16) that extend on the division area (12), and each mat (18) Connection wiring between each circuit element within is basically performed by first layer wiring.

After the second layer wiring, the division line (17) and division area (
12) and is mainly used to form signal transmission wiring between each mat (18).

Note that the divided area < 12) is sometimes divided by each division line (17).
Also extend parallel to. This is due to the positional constraints of the VCC electrode pad (19) and ground electrode pad (20) in relation to the package bin arrangement requirements, and the adjacent mat (
18) or between each mat (18) if there is a relationship that is particularly desired to be spaced apart in circuit functional blocks. In Figure 1, the reason for the former is between mats D and E, and mat M
The reason for the latter is between and N. A V is provided near the end of the divided region (12a) extending in parallel. V from the 0 electrode pad (19〉) and the ground pad (20〉) respectively.
The CC line 15) and the ground line (16) are routed, and then they are routed over the divided area (12) that crosses the center of the semiconductor chip (11) to form each pine l-(18).
connected to circuit elements inside.

When functional circuit blocks are housed in the semiconductor chip (11) in which the element formation area is divided into a large number of mats (18) in this way, each circuit block is housed as follows.

First, since the mat (18) is designed to have a size that can accommodate an arbitrary fixed number of elements, the circuit block is divided into the fixed number of elements. For example, if the size of the mat (18) is for storing 100 elements and the circuit block is about 270 elements, prepare three mats (18) and store 100 elements each.
Classify using 00 elements as a guide. Of course, capacitors, etc. that occupy a large area should be taken into consideration. Then, the circuit elements are stored in each mat (18) according to the above classification, and the circuit elements are stored in each mat (18).
8) Connection wiring and elements between circuit elements such as NPN-PNP transistors, diodes, resistors, and capacitors housed in ■. . The connection wiring with the ground lines (15) and (16) is terminated at the first wiring layer. After repeating this process and completing the pattern design for all the mats (18), the three mats (18) are placed adjacent to each other, and the electrical connection between each mat (18) is established by wiring from the second layer onwards. By making connections, functional circuit blocks are constructed.

After storing all the circuit blocks in the mat (18), combine all the mats (18) and design the entire IC by making electrical connections between each circuit block using the second and subsequent wiring layers. do.

According to this configuration, by storing each circuit block in an integer number of mats, each circuit block can be designed, and the circuit block can be divided into a fixed number of elements to be stored on the mat (1
8) You will be able to design each case. Therefore, it is possible to design each circuit block in parallel, and the design period can be significantly shortened. Further, since circuit changes can be made for each circuit block and each mat, there is no need to change the design of the entire IC.

As shown in FIG. 2, a divided area (12) divides the semiconductor chip (11) into a first area (13) consisting of mats A-J and a second area (14) consisting of mats A-J.
A dummy island (
21). Since this dummy island (21) is formed by an epitaxial region completely surrounded by a highly doped isolation region connected to a semiconductor substrate to which a ground potential is applied, each dummy island (21) is electrically independent from the others. do. In addition, as shown in Figure 1, the first area < 13)
The divided area (12a) which divides the area into matte A-D and M-N) E-J groups and the second area (B) into matte-M
A divided area (1
2a), a dummy island (21) is also extended to each divided region (12a).

Dummy island (21) formed in divided area (12)
The cross-sectional structure of is shown in FIG. (22) is a P-type semiconductor substrate, (23) is an N-type epitaxial layer, and as mentioned above, the dummy island (21) is a P+ type isolation region (
It is formed by an N-type epitaxial layer (23) surrounded by (24). The surface of the dummy island (21) is covered with an oxide film (25), and the first wiring layer thereon has a VCC or ground line (
A plurality of mats (15) and (16) extend in parallel, and a signal transmission wiring (27) connecting each mat (18) via an interlayer insulating film (26) is further provided in the second wiring layer above the wiring. ) or a portion of the VCC or ground wiring (15) (16) extends.

According to such a configuration, the first and second regions (13) (14> divided by the divided region (12) are separated from each other by the divided region (12).
Since the distance increases by the area occupied by , the layer resistance (28) of the substrate (22) and the layer resistance (28) of the epitaxial layer (23)
By increasing the resistance component due to 29), the coupling between the first region (13) and the second region (14) can be made loose.

In addition, if the dummy island (21) is made into a multilayer structure using the area occupied by the divided region (12), in addition to the resistance component (29) formed by the layer resistance of the epitaxial layer (23), the separated region (24) P-type region and dummy island (21
Since a plurality of potential barriers are formed by the PN junctions formed by the N-type regions of ), the resistance component can be increased and the coupling between the first and second regions (13) and (14) can be made even rougher. Furthermore, since the potential barrier can also be considered as a junction capacitance (30) due to a PN junction, V extending over the divided region (12).

Using the C line (15), connect the N1 type contact region (3
1) Power supply potential ■ to the dummy island (21〉) through.

By applying C, the dummy island (21) can be grounded in an alternating current manner, the junction capacitance (30) can be increased, and the resistance component can be increased. Third
In the example shown in the figure, the dummy island (21) has a triple structure, with VCC applied to the central dummy island (21), and the dummy islands <21> on both sides floating to which no potential is applied. Generally dummy island (21
) has a multiple structure, the first and second regions (13) (1
Since the bonding in step 4) can be made coarse, the separation area (24) is formed as many times as possible within the area occupied by the division area (12), with the area occupied by the separation area (24) being the minimum line width of the process.

As explained above, by forming the dummy island (21) in the divided area (12), the first and second areas (1)
4) Since the coupling can be made coarse, one embodiment will be described below in which an FM/AM tuner as shown in FIG. 5 is formed on the semiconductor chip (11) by taking advantage of this advantage.

In Fig. 1 or Fig. 2, the AM tuner circuit (5) pro-nk is connected to the four mats (18) of mats A-D, and the FM tuner circuit (5) is installed to the five mats (18) of mats E-I. The amplifier circuit (2) block is installed in one 1 (i- mat (18)) of mat J, and the FM front-end circuit ( 1) Blocks are noise canceling circuits on the three mats (18) of mats NP (2) Blocks are multiplex circuits on the four mats (18) of mats Q-T (4> blocks are each circuits) It is stored in each block.

The FM front end circuit (1) housed in the mat at -M is tuned by the antenna (6) and a tuning circuit (not shown).
It has a function of frequency-converting an F-fold signal into an intermediate frequency signal of 10.7 MHz by mixing it with a local oscillation frequency signal generated by the RF-multiply signal local oscillation circuit in a mixing circuit and outputting the signal. This circuit is a few microvolts (μ
This circuit handles signals ranging from an extremely low level (V) to several volts (V), so it is extremely sensitive to interference signals from other circuit blocks. Furthermore, since the local oscillation circuit itself oscillates and emits unnecessary radiation, it is a circuit that should be separated from other circuit blocks as much as possible.

-j5, FM/IF amplifier circuit installed in Matsu l-E~■ (
2) has the functions of amplifying and amplitude limiting the intermediate frequency signal with a limiter-amplifier circuit, and demodulating it into a composite signal by detecting it with a detection circuit. This circuit handles a frequency signal of 10.7 MHz, which is relatively similar to the frequency handled by the FM front end M path (1), and also amplifies and handles signals with large amplitude levels, so the FM/IF amplifier circuit (2) The leakage current from the FM front end M
When the FM front end M path (1) is reached, the RF multiplied signal is drowned out by mutual signal interference, and the circuit becomes unstable, especially when the input level is extremely low, and in severe cases it will oscillate. The combination of 1) and the FM/IF amplifier circuit (2), especially the local oscillation circuit and the limiter amplifier circuit, is a combination that must be strongly separated from each other.

On the other hand, the multiplex circuit (4) housed in the mat Q-T
converts the sum signal (L+R) and difference signal (L-R) in the composite signal into left and right stereo signals using a 38KHz switching signal generated in response to a 19K)lz stereo pilot signal also included in the composite signal. It has a stereo demodulation function that separates into (L and R).

Since this circuit uses the switching operation of a transistor to generate the 38 KHz switching signal, it is likely to generate switching noise along with the operation. For example, a PLL (phase locked loop) circuit consisting of a phase comparator, a low-pass filter, a voltage controlled oscillator, and a plurality of frequency dividers is used as the circuit for generating the switching signal. Therefore, if possible, it is a circuit that should be separated from the FM front end M path (1) and the FM-IF amplifier circuit (2).

In addition, the noise canceling circuit (3
) has a function of removing pulse noise when it is superimposed on the composite signal. This circuit does not particularly handle high-frequency signals or generate switching noise.

Furthermore, AM tuner circuit (5) housed in mat A-D
has a function of selecting AM broadcasting and outputting an audio (AF) signal. Generally, the amount of FM broadcasting received19- and AM reception are completely switched by an external control signal, and the frequency is around several hundred KHz, so A
M tuner circuit (5) and FM front end M path (1)
It can be assumed that there is no signal interference with the FM/IF amplifier circuit (2).

According to such a configuration, the FM front end M path (1) and F
The M-IF amplifier circuit (2) is connected to the first and second flJ[(
13) (14) pine) (1B>), so they can be separated by the distance of the divided area (12), and
By increasing the impedance due to the dummy island (21), the coupling between the two through the epitaxial layer (23) can be made even rougher. Therefore, FM front end M
It becomes possible to integrate the circuit (1) and the FM/IF amplifier circuit (2) into one chip while preventing mutual signal interference. Also,
Altibrex circuit that tends to generate switching noise (
4), for the FM-IF amplifier circuit (2), the divided area (12> and the dummy island (21) are sandwiched between them, so the F
Since the noise canceling circuit (3) block and the dummy island (21) are interposed between the M front end circuit (1) and the noise canceling circuit (3) block, signal interference can be prevented by coupling with each circuit.

By the way, the FM front end M path (1) and the FM-
In addition to the relationship with the IF amplifier circuit (2), interference occurs via the substrate (22>) between adjacent mats (18), between each circuit element formed within the mat (18>), etc. This interference is mainly caused by a nok current to the substrate (22), and circuit elements that tend to leak current dC include capacitors, NPN-PNP transistors with saturated operation, and N-type epitaxial layer (23) based circuit elements. Lateral PNP transistor and lateral PNP)
Examples include IIL that uses a transistor as an injector,
The potential of the substrate (22) is increased not only in adjacent circuit elements but also in distant circuit elements, making the circuit operation unstable.

To prevent such leakage current, the separation area (
24) Suction electrode (3) that makes ohmink contact with the surface
2) will be dealt with. That is, as shown in FIG. 4, ohmink contact is made between circuit elements or groups of circuit elements that are expected to cause interference in the immediate vicinity of the circuit elements from which the leakage current is likely to flow, through contact holes (33). ,
Ground line (16) forming section line (17)
It is connected to and grounded. In addition, the plot line (17
) by reusing the ground line (16) itself as the suction electrode (32), each mat (18
) and prevents an increase in chip size.

The ground line (16) to which the suction electrode (32) is connected
) are divided or shared depending on the magnitude of the leaked current and whether or not the ground line (16) is allowed to have a common impedance. Therefore, a plurality of Guérande lines 16) extend over the divided area (12). For example, in Figure 4, FM is placed on mat E.
・Since the capacitor elements constituting the IF amplifier circuit (2) are arranged in a concentrated manner, it is predicted that leakage to the substrate (22) will be extremely large, so the ground line (16) forming the partition line (17) ) itself as a suction electrode (32), a ground line (16) is extended so that the entire mat E is surrounded by the suction electrode (32>), and the outer periphery of the chip (11) is further extended to form a ground electrode. Pad (2
0).

The suction electrode (32) in the area of the mat E is to protect the capacitor elements from interference with each other.

The extraction electrode (32) in the area of the mat G is provided in the immediate vicinity of the circuit element from which the leakage current tends to flow out, and since the absolute value of the leakage current is small, the extraction electrode (32) is It is shared with the ground line 6) which provides the ground potential for circuit operation. Since the circuit elements formed on the mat F and mat G functionally allow a common impedance, and the absolute value of the leakage current is not very large, these ground lines (16
) are combined into one on the divided region (12) and connected to the ground electrode pad (20>).

(g) As described in detail, the present invention is based on the mat 8) and stores each circuit block in an integer number of areas of the mat (18), so a pattern can be designed for each mat (18). , it has the advantage that the entire IC layout can be realized arbitrarily by combining the designed matte boards 18〉.It also has the advantage that each mat (18) can be designed in parallel.Therefore, the design period for the entire IC can be reduced. In addition to shortening the process, when designing a model with a different circuit function, the mat of the changed part (18)
Only one mat (18) needs to be designed, and the remaining mat (18) can be used while maintaining the reliability of the previous model, which has the advantage of greatly shortening the design period required for model development.

Then, in order to form the above-mentioned mat (18) and the mat (
V for providing operating power to the circuit elements housed in 1B).

Since the occupied area of the divided area (12) where the 0 line (15) and the ground line (16) are extended is used, and the dummy island (21) is provided in this area, the occupied area can be used effectively, and the divided area The first and second regions (13) and (14) of the substrate (
22) can make the bond loose. Therefore, when forming circuit blocks on the same chip (11) that have different frequencies and signal levels and are likely to cause signal interference, these circuit blocks are separated into the first and second regions (13) and (14). By combining the mats (18) in this manner, there is an advantage that a high-performance IC can be realized that prevents mutual signal interference. In addition, by utilizing the above advantages, the FM front end circuit (
By integrating 1) and the FM-IF amplifier circuit (2) into one chip, there is an advantage that a cheaper and higher performance FM tuner can be provided.

Furthermore, since the suction electrode <32) is provided in the vicinity of the circuit element in the mat (18) that is likely to cause leakage current, the leakage current to the substrate (22) can be immediately sucked out, and the leakage current between adjacent circuit elements can be immediately sucked out. Interference can be prevented.

In addition, a suction electrode (32) is provided between adjacent mats (18).
), the leakage current that could not be removed by the suction electrode (32) in the mat (18) and the leakage current from other circuit elements is sucked out, and interference between adjacent mats (18) is prevented. It can be prevented. Furthermore, a ground line (16) for forming a division line (17) is provided.
) as the suction electrode (32), there is also the advantage that the occupied area can be used efficiently.

[Brief explanation of the drawing]

1 and 2 are plan views for explaining the present invention, FIGS. 3 and 4 are a sectional view and a plan view of essential parts, respectively, for explaining the present invention, and FIG. 5 is an FM/ FIG. 2 is a circuit diagram for explaining an AM tuner circuit. (12) is the divided area, (13) and (14) are the first and second
(15) and (16) are VCC and ground lines, (18) is a mat, (21) is a dummy island, (24) is a P+ type isolation region, and (32) is an extraction electrode.

Claims (1)

Scope of Claims: (1) The semiconductor chip is divided into a first and second region by a dividing region extending substantially in a straight line in the center of the semiconductor chip, and a power line is connected in a direction perpendicular to the dividing region. dividing the first and second regions into a plurality of regions of substantially the same size by arranging a plurality of division lines in which pairs of ground lines are extended, each region being made into a mat;
Each functional circuit block is stored in an integral number of mats,
A power supply or ground line individually connected to the electrode pad is extended over the divided region, and one or more dummy islands surrounded by separated regions of the same conductivity type connected to the semiconductor substrate are provided in the divided region. A semiconductor integrated circuit characterized by being provided with. (2> The semiconductor chip is divided into a first and second region by a division region extending in a substantially straight line through the center of the semiconductor chip, and a power supply line and a ground line are extended in pairs in a direction orthogonal to the division region. dividing the first and second regions into a plurality of regions of substantially the same size by arranging a plurality of partition lines in parallel, each region being made into a mat;
A high frequency circuit block is stored using an integral number of mats in either the first or second area, and a circuit block having a different function and frequency from the high frequency circuit block is stored using an integral number of mats in the other area. a dummy island in which a plurality of power or ground lines are housed and connected to the electrode pads individually on the divided region, and the divided region is surrounded by a separated region of the same conductivity type connected to a semiconductor substrate; 1. A semiconductor integrated circuit characterized in that a semiconductor integrated circuit is provided in a single layer or in multiple layers. (3) The high frequency circuit block is a front end circuit including at least a local oscillation circuit, and the circuit block having a different function and frequency is an intermediate frequency amplification circuit including at least an amplitude limiting circuit. 2
The semiconductor integrated circuit described in . (4) The semiconductor chip is divided into a first and second region by a dividing region extending in a substantially straight line through the center of the semiconductor chip, and a power supply line and a ground line are extended in pairs in a direction perpendicular to the dividing region. dividing the first and second regions into a plurality of regions of substantially the same size by arranging a plurality of partition lines in parallel, each region being made into a mat;
Circuit blocks with different functions and frequencies are housed in an integral number of mats, and a suction electrode is provided at a desired location in each mat to make ohmic contact with the surface of a separated region of the same conductivity type connected to a semiconductor substrate, and the divided region is A plurality of ground lines connected to the suction electrode are provided on the top for different purposes, and are individually connected to one or more ground electrode pads, and a dummy island surrounded by the separation area is provided in the divided area in one or more layers. A semiconductor integrated circuit characterized by being formed in multiple layers. (5) A high frequency circuit block is housed in either the first or second area, and a circuit block having a different function and frequency from the high frequency circuit block is housed in the other area. The semiconductor integrated circuit described in . (6) The high frequency circuit block is a front end circuit including at least a local oscillation circuit, and the circuit block having a different function and frequency is an intermediate frequency amplifier circuit including at least an amplitude limiting circuit. The semiconductor integrated circuit according to item 5. (7) The semiconductor integrated circuit according to claim 4 or 5, wherein the ground line that partitions the mat and the suction electrode are constituted by a common electrode.